Showing results for "IC"
Provide a framework for choosing IC vs management: strengths, career outcomes, and risk tradeoffs. Include a decision worksheet and a 6-month experiment plan.
Author: Assistant
Category: global-business-advice | Model: gpt-4o
Create a 1:1 framework: agenda, coaching questions, blockers, growth, and feedback. Include templates for junior ICs, senior ICs, and managers across regions.
Author: Assistant
Category: global-business-advice | Model: gpt-4o
Make a 60-second educational story from wafer to packaged chip (generic). Include clean factory visuals, microscope shots, and safe, non-sensitive explanations. Provide prompts for Sora and Gemini.
Author: Assistant
Category: tech-education-video | Model: gpt-4o
You are a landing assistant. Provide step-by-step arrival flows: immigration, baggage, SIM/eSIM or Wi-Fi rental, IC card purchase, cash withdrawal, and best first-ride options into central Tokyo or Os...
Author: Assistant
Category: arrival | Model: gpt-4o
日本語で12個の一言ジョーク（電車の時間・駅ホーム・ICカード）。優しく、政治NG、ステレオタイプ禁止。各ジョークは{setup_ja,punchline_ja,setup_en,punchline_en,locale:'ja-JP'}。各≤120字。
Author: Assistant
Category: humor | Model: gpt-4o
You are a rail guide. Explain when to use IC cards vs paper tickets; how to top up, tap in/out, and use mobile wallets. Add example rides for Tokyo, Yokohama, Kyoto, Osaka, and typical fares. Include ...
Author: Assistant
Category: transport | Model: gpt-4o
Act as a shopper’s ally. Explain cash vs cards vs mobile IC payments, where ATMs with foreign cards work, tax-free rules (passport, minimums), and packaging for carrying goods on trains.
Author: Assistant
Category: shopping-basics | Model: gpt-4o
Design a yield-ramp methodology: defect density assumptions, critical area analysis, redundancy strategies, pattern-matching for systematic defects, Pareto dashboards, and wafer map analytics. Include...
Author: Assistant
Category: chip-design | Model: gpt-4
Propose a 3D-IC plan with TSVs: mechanical stress modeling, keep-out zones, coupling mitigation, thermal stack design, test access, and yield strategy. Include co-simulation setup and acceptance thres...
Author: Assistant
Category: chip-design | Model: gpt-4
Act as a PnR lead at 2nm. Propose a floorplan strategy for a large SoC with multiple GAA CPU/GPU clusters: die size estimate, aspect ratio, macro placement heuristics, channel widths, hierarchy partit...
Author: Assistant
Category: chip-design | Model: gpt-4
Design a CTS plan that balances skew, latency, and power for a 1.2 GHz domain with multiple clock gating islands. Include buffer/inverter choices, mesh vs spine tradeoffs, useful-skew targets, OCV der...
Author: Assistant
Category: chip-design | Model: gpt-4
Create a power integrity plan using backside power delivery and buried power rails. Include PDN topology, stripe pitch, via stacking, decap budgeting, vectorless vs vector-based IR analysis, EM rules,...
Author: Assistant
Category: chip-design | Model: gpt-4
Draft a DRC/LVS closure strategy under EUV and multi-patterning rules. Include hotspot classes, recommended routing rules, antenna fixes, via redundancy, density/slotting, guard rings, and signoff wai...
Author: Assistant
Category: chip-design | Model: gpt-4
Produce a timing closure plan across slow/fast corners using POCV/SSTA. Define derate tables, path grouping, crosstalk analysis, useful skew usage, setup/hold repair ordering, and ECO guidelines. Incl...
Author: Assistant
Category: chip-design | Model: gpt-4
Write a power architecture using UPF with 3 voltage islands, DVFS, and retention strategies. Provide power-state tables, isolation/level-shifter rules, retention flop mapping, and power-sequencing tim...
Author: Assistant
Category: chip-design | Model: gpt-4
Propose a chiplet SoC using UCIe 1.1 over 2.5D interposer: partitioning rationale, die-to-die bandwidth/latency budget, PHY choices, protocol mapping, cache-coherency options, test strategy, and yield...
Author: Assistant
Category: chip-design | Model: gpt-4
Create an HBM3E integration plan: stack selection, channel topology, timing margins, package escape routing, SI/PI simulations, PDN target impedance, thermal throttling strategy, and test hooks. Outpu...
Author: Assistant
Category: chip-design | Model: gpt-4
Outline a custom SRAM plan (6T/8T): read/write stability analysis, Vmin targets, assist techniques, redundancy/repair, ECC options, leakage control, and BIST. Provide SPICE corners, Monte Carlo setup,...
Author: Assistant
Category: chip-design | Model: gpt-4
For a 12-bit SAR ADC and PLL, provide layout tactics: common-centroid matching, guard rings, substrate isolation, well taps, shielding, dummy fills, coupling control, and latch-up prevention. Include ...
Author: Assistant
Category: chip-design | Model: gpt-4
Develop a DFT plan: scan compression goals, LBIST architecture, MBIST algorithms for SRAM/ROM, boundary scan, JTAG access, test time/cost model, and fault coverage targets. Provide patterns and bring-...
Author: Assistant
Category: chip-design | Model: gpt-4
Draft a safety and reliability plan: FIT targets, FMEDA, ASIL decomposition, safety mechanisms, aging stress, ESD/EMC design, and qualification flow (AEC-Q100). Provide safety case artifacts and test ...
Author: Assistant
Category: chip-design | Model: gpt-4
Create a litho/RET action plan for EUV with stochastic defect mitigation: OPC hotspots, tip-to-tip spacing, jog rules, forbidden pitches, cut/block layer strategies, and in-design checking. Provide a ...
Author: Assistant
Category: chip-design | Model: gpt-4
Propose a co-design flow with package, board, and die PDN: bump map optimization, RDL planning, target impedance vs frequency, thermal stack-up, and coupled SI/PI/thermal simulations. Include signoff ...
Author: Assistant
Category: chip-design | Model: gpt-4
Build a reliability budget: device degradation models, BTI guardbands, HCI stress points, TDDB oxide limits, EM lifetimes, and burn-in strategy. Provide a reliability dashboard and field-return feedba...
Author: Assistant
Category: chip-design | Model: gpt-4
Define a push-button signoff pipeline: reproducible EDA containers, golden rule decks, regression checklists, run orchestration, artifact retention, and ECO automation for timing/IR/DRC. Output a CI/C...
Author: Assistant
Category: chip-design | Model: gpt-4
Create a silicon security plan: logic locking insertion points, scan chain protections, PUF selection and enrollment, side-channel mitigation, secure boot root-of-trust, and anti-tamper sensors. Provi...
Author: Assistant
Category: chip-design | Model: gpt-4
Design a pre-silicon validation flow using emulation and FPGA protos: partition strategy, speed/visibility tradeoffs, trace buffers, stimulus generation, coverage closure, and HW/SW co-verification mi...
Author: Assistant
Category: chip-design | Model: gpt-4
Outline a high-speed SerDes design: channel specs, CTLE/DFE equalization, CDR architecture, TX FIR taps, jitter budget, compliance masks, and IBIS-AMI modeling. Include lab validation steps and BER ta...
Author: Assistant
Category: chip-design | Model: gpt-4
Propose a mmWave beamformer: phase shifter topology, PA/LNA linearity targets, NF, LO distribution, antenna-in-package constraints, calibration loops, and EVM/ACL metrics. Provide layout isolation gui...
Author: Assistant
Category: chip-design | Model: gpt-4
Create a PLL plan: loop filter design, VCO selection, fractional-N spur mitigation, jitter decomposition, phase noise spec allocation, and supply-noise rejection. Provide simulation setups and accepta...
Author: Assistant
Category: chip-design | Model: gpt-4
Compare SAR, pipeline, and sigma-delta ADCs for a sensor hub. Include FoM, resolution/SNR targets, sampling rate, power, area, calibration needs, and DFT hooks. Output a recommendation with risk log a...
Author: Assistant
Category: chip-design | Model: gpt-4
Provide a timing ECO guide: buffer sizing rules, cell Vt swaps, re-route constraints, shielding for aggressors, hold-fix ordering, and checks to avoid IR/EM regression. Include a before/after metrics ...
Author: Assistant
Category: chip-design | Model: gpt-4
Define a library characterization plan at low voltage (0.6 V): corners, CCS/ECSM models, NLDM fallback, slew/load grids, OCV views, and QA checks. Provide Liberty snippets and validation tests.
Author: Assistant
Category: chip-design | Model: gpt-4
Create an adoption plan for backside power and buried rails on a next-gen CPU tile: design rule deltas, floorplan implications, timing/power impact, tool flow changes, risk mitigation, and fab engagem...
Author: Assistant
Category: chip-design | Model: gpt-4