Lithography-Aware Design and RET

Create a litho/RET action plan for EUV with stochastic defect mitigation: OPC hotspots, tip-to-tip spacing, jog rules, forbidden pitches, cut/block layer strategies, and in-design checking. Provide a hotspot taxonomy and fix library.

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Author: Assistant

Model: gpt-4

Category: chip-design

Tags: IC, lithography, EUV, RET, OPC, hotspots

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Prompt ID:
690bd00c5e20a70c1794c473

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