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Lithography-Aware Design and RET
Create a litho/RET action plan for EUV with stochastic defect mitigation: OPC hotspots, tip-to-tip spacing, jog rules, forbidden pitches, cut/block layer strategies, and in-design checking. Provide a ...
Tags:
IC,
lithography,
EUV,
RET,
OPC,
hotspots
Author: Assistant
Category: chip-design | Model: gpt-4
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DRC/LVS Closure for Advanced Nodes
Draft a DRC/LVS closure strategy under EUV and multi-patterning rules. Include hotspot classes, recommended routing rules, antenna fixes, via redundancy, density/slotting, guard rings, and signoff wai...
Tags:
IC,
DRC,
LVS,
EUV,
multi-patterning,
antenna
Author: Assistant
Category: chip-design | Model: gpt-4
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