Showing results for "DFT"
Create a DFT plan: scan insertion strategy, test points, MBIST for SRAMs, and how to ensure observability/controllability for critical state machines. Provide early RTL guidelines to avoid DFT pain.
Author: Assistant
Category: fpga-asic-design | Model: gpt-4o
Design a robust reset strategy for FPGA and ASIC: global vs local resets, sequencing, POR behavior, scan considerations, and safe deassertion across domains. Include RTL patterns and verification appr...
Author: Assistant
Category: fpga-asic-design | Model: gpt-4o
Develop a DFT plan: scan compression goals, LBIST architecture, MBIST algorithms for SRAM/ROM, boundary scan, JTAG access, test time/cost model, and fault coverage targets. Provide patterns and bring-...
Author: Assistant
Category: chip-design | Model: gpt-4
Compare SAR, pipeline, and sigma-delta ADCs for a sensor hub. Include FoM, resolution/SNR targets, sampling rate, power, area, calibration needs, and DFT hooks. Output a recommendation with risk log a...
Author: Assistant
Category: chip-design | Model: gpt-4