Showing results for "signoff"
Design an agent to tune security headers and CSP safely: staged enforcement, report-only mode, breakage monitoring, and rollback. Require security team sign-off.
Author: Assistant
Category: safe-self-improving-ai | Model: gpt-5.2
Create a safety case template per capability: hazards, mitigations, tests, monitoring, rollback, and residual risk. Require evidence links and sign-off rules.
Author: Assistant
Category: safe-self-improving-ai | Model: gpt-5.2
Create a final assembly sign-off checklist for a custom car, motorcycle, or bicycle: fasteners, wiring, brakes, controls, fluids, clearances, road/ride test, and documentation.
Author: Assistant
Category: vehicle-engineering-mechanics | Model: GPT-5.2
Create a power intent plan: power domains, isolation, retention, level shifters, and power state sequencing. Provide a UPF/CPF concept spec and integration risks for verification and signoff.
Author: Assistant
Category: fpga-asic-design | Model: gpt-4o
Define a push-button signoff pipeline: reproducible EDA containers, golden rule decks, regression checklists, run orchestration, artifact retention, and ECO automation for timing/IR/DRC. Output a CI/C...
Author: Assistant
Category: chip-design | Model: gpt-4
Outline a custom SRAM plan (6T/8T): read/write stability analysis, Vmin targets, assist techniques, redundancy/repair, ECC options, leakage control, and BIST. Provide SPICE corners, Monte Carlo setup,...
Author: Assistant
Category: chip-design | Model: gpt-4
Propose a co-design flow with package, board, and die PDN: bump map optimization, RDL planning, target impedance vs frequency, thermal stack-up, and coupled SI/PI/thermal simulations. Include signoff ...
Author: Assistant
Category: chip-design | Model: gpt-4
Draft a DRC/LVS closure strategy under EUV and multi-patterning rules. Include hotspot classes, recommended routing rules, antenna fixes, via redundancy, density/slotting, guard rings, and signoff wai...
Author: Assistant
Category: chip-design | Model: gpt-4
Create a power integrity plan using backside power delivery and buried power rails. Include PDN topology, stripe pitch, via stacking, decap budgeting, vectorless vs vector-based IR analysis, EM rules,...
Author: Assistant
Category: chip-design | Model: gpt-4