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Showing results for "SerDes"
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SerDes-Friendly Packetization and Framing
Create a packetization/framing scheme for high-speed links: framing, CRC, alignment markers, credit/backpressure, and error recovery. Provide RTL module boundaries and test plan.
Tags:
SerDes,
packets,
CRC,
framing,
links,
verification
Author: Assistant
Category: fpga-asic-design | Model: gpt-4o
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112G/224G SerDes PHY Design Plan
Outline a high-speed SerDes design: channel specs, CTLE/DFE equalization, CDR architecture, TX FIR taps, jitter budget, compliance masks, and IBIS-AMI modeling. Include lab validation steps and BER ta...
Tags:
IC,
SerDes,
PHY,
high-speed,
signal-integrity,
IBIS-AMI
Author: Assistant
Category: chip-design | Model: gpt-4
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