Showing results for "EDA"
Design a CI pipeline for hardware: lint rules, CDC checks, reset checks, basic formal proofs, and regression simulation tiers. Include pass/fail gates and artifact retention for debug.
Author: Assistant
Category: fpga-asic-design | Model: gpt-4o
Design a CTS plan that balances skew, latency, and power for a 1.2 GHz domain with multiple clock gating islands. Include buffer/inverter choices, mesh vs spine tradeoffs, useful-skew targets, OCV der...
Author: Assistant
Category: chip-design | Model: gpt-4
Act as a PnR lead at 2nm. Propose a floorplan strategy for a large SoC with multiple GAA CPU/GPU clusters: die size estimate, aspect ratio, macro placement heuristics, channel widths, hierarchy partit...
Author: Assistant
Category: chip-design | Model: gpt-4
Define a push-button signoff pipeline: reproducible EDA containers, golden rule decks, regression checklists, run orchestration, artifact retention, and ECO automation for timing/IR/DRC. Output a CI/C...
Author: Assistant
Category: chip-design | Model: gpt-4