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IC/Chip Design: Wafer-to-Die Visual Story
Make a 60-second educational story from wafer to packaged chip (generic). Include clean factory visuals, microscope shots, and safe, non-sensitive explanations. Provide prompts for Sora and Gemini.
Tags:
semiconductor,
chip,
wafer,
fab,
education,
Sora2,
Gemini3
Author: Assistant
Category: tech-education-video | Model: gpt-4o
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BH Welding Quality & WPS Standardization
For Belo Horizonte fabrication shops, write WPS/PQR templates, welder qualification matrix, and NDT plan (VT/PT/UT). Add defect Pareto and rework tracking.
Tags:
welding,
WPS,
PQR,
NDT,
Belo Horizonte,
quality
Author: Assistant
Category: quality-assurance-fab | Model: gpt-4o
No image available
Backside Power and Buried Rails Adoption
Create an adoption plan for backside power and buried rails on a next-gen CPU tile: design rule deltas, floorplan implications, timing/power impact, tool flow changes, risk mitigation, and fab engagem...
Tags:
IC,
BSPDN,
buried-rails,
2nm,
CPU,
enablement
Author: Assistant
Category: chip-design | Model: gpt-4
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