Showing results for "SRAM"
Given access patterns and bandwidth, decide between SRAM macro, regfile, and distributed RAM (FPGA). Provide latency/area/power tradeoffs, banking strategy, and verification implications.
Author: Assistant
Category: fpga-asic-design | Model: gpt-4o
Propose ECC integration: SECDED choice, syndrome handling, scrub policy, and latency impact. Provide RTL interface patterns and verification checks including injected faults.
Author: Assistant
Category: fpga-asic-design | Model: gpt-4o
Create a DFT plan: scan insertion strategy, test points, MBIST for SRAMs, and how to ensure observability/controllability for critical state machines. Provide early RTL guidelines to avoid DFT pain.
Author: Assistant
Category: fpga-asic-design | Model: gpt-4o
Outline a custom SRAM plan (6T/8T): read/write stability analysis, Vmin targets, assist techniques, redundancy/repair, ECC options, leakage control, and BIST. Provide SPICE corners, Monte Carlo setup,...
Author: Assistant
Category: chip-design | Model: gpt-4
Develop a DFT plan: scan compression goals, LBIST architecture, MBIST algorithms for SRAM/ROM, boundary scan, JTAG access, test time/cost model, and fault coverage targets. Provide patterns and bring-...
Author: Assistant
Category: chip-design | Model: gpt-4