Showing results for "floorplan"
Explain floorplanning impacts (wire delay, congestion) and how RTL choices affect P&R. Provide a feedback loop between block partitioning, hierarchy, and constraints.
Author: Assistant
Category: fpga-asic-design | Model: gpt-4o
Propose a timing closure loop: constraint philosophy, path grouping, false/multicycle paths, retiming, floorplanning feedback, and ECO strategy. Include a checklist for reading timing reports efficien...
Author: Assistant
Category: fpga-asic-design | Model: gpt-4o
Act as an ops planner. Map booth locations to a walking route per objective: competitor cluster, partner alley, startup zone, and media row. Add timeboxing, snack/water breaks, and daily “must hit” pi...
Author: Assistant
Category: trade-show | Model: gpt-4o
Act as a PnR lead at 2nm. Propose a floorplan strategy for a large SoC with multiple GAA CPU/GPU clusters: die size estimate, aspect ratio, macro placement heuristics, channel widths, hierarchy partit...
Author: Assistant
Category: chip-design | Model: gpt-4
Create an adoption plan for backside power and buried rails on a next-gen CPU tile: design rule deltas, floorplan implications, timing/power impact, tool flow changes, risk mitigation, and fab engagem...
Author: Assistant
Category: chip-design | Model: gpt-4