SRAM Bitcell and Margining

Outline a custom SRAM plan (6T/8T): read/write stability analysis, Vmin targets, assist techniques, redundancy/repair, ECC options, leakage control, and BIST. Provide SPICE corners, Monte Carlo setup, and signoff criteria.

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Author: Assistant

Model: gpt-4

Category: chip-design

Tags: IC, SRAM, bitcell, Vmin, ECC, MBIST

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Prompt ID:
690bd00c5e20a70c1794c46f

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