Showing results for "FPGA-prototype"
Help me choose a controls layout: symmetry, stick height, trigger travel, back buttons, and hall effect options. Provide a prototype checklist and iteration plan.
Author: Assistant
Category: handheld-pc-makers | Model: GPT-5.2
Create a cost control plan for makers: stage gates, “must-have vs nice-to-have,” reuse parts, and how to decide when to stop iterating.
Author: Assistant
Category: handheld-pc-makers | Model: GPT-5.2
Create an iteration plan: V0 proof-of-concept, V1 usable prototype, V2 refinement. Include acceptance criteria, testing checklists, and what to learn each stage.
Author: Assistant
Category: handheld-pc-makers | Model: GPT-5.2
Design a playbook for taking AGI-generated prototypes to production safely: testing, monitoring, compliance, and user research. Include timelines and roles.
Author: Assistant
Category: future-monetization | Model: gpt-5.2
Propose product ideas that combine AGI design with physical constraints (sensors, wearables, robotics). Include prototyping plan, BOM thinking, and go-to-market.
Author: Assistant
Category: future-monetization | Model: gpt-5.2
Provide a decision framework for choosing an engine: target platforms, networking, tooling, team skillset, and performance constraints. Include a phased prototyping plan and risk register.
Author: Assistant
Category: gaming-metaverse | Model: gpt-5.2
Generate a CDC audit checklist: async FIFO design, synchronizer placement, handshake protocols, reset crossings, multi-bit control, and metastability risk scoring. Provide recommended assertions and t...
Author: Assistant
Category: fpga-asic-design | Model: gpt-4o
Design a UVM environment: agents, scoreboards, reference models, sequence layering, coverage model, and CI integration. Include best practices for reproducibility and debug speed.
Author: Assistant
Category: fpga-asic-design | Model: gpt-4o
Create a power intent plan: power domains, isolation, retention, level shifters, and power state sequencing. Provide a UPF/CPF concept spec and integration risks for verification and signoff.
Author: Assistant
Category: fpga-asic-design | Model: gpt-4o
Propose a timing closure loop: constraint philosophy, path grouping, false/multicycle paths, retiming, floorplanning feedback, and ECO strategy. Include a checklist for reading timing reports efficien...
Author: Assistant
Category: fpga-asic-design | Model: gpt-4o
Write scalable SDC patterns: generated clocks, clock uncertainty, I/O constraints, clock groups, and exceptions. Include best practices to avoid over-constraining and how to validate constraints with ...
Author: Assistant
Category: fpga-asic-design | Model: gpt-4o
Build a performance model: cycles per operation, pipeline occupancy, memory stalls, and bandwidth ceilings. Output a spreadsheet-ready formula set and guidance on calibrating with simulation.
Author: Assistant
Category: fpga-asic-design | Model: gpt-4o
Explain floorplanning impacts (wire delay, congestion) and how RTL choices affect P&R. Provide a feedback loop between block partitioning, hierarchy, and constraints.
Author: Assistant
Category: fpga-asic-design | Model: gpt-4o
Provide a deadlock analysis method: dependency graph, buffer ordering, and escape paths. Include a checklist for AXI + DMA + multiple FIFOs systems.
Author: Assistant
Category: fpga-asic-design | Model: gpt-4o
Create a side-channel awareness checklist: data-dependent switching, timing variability, and observable control flow. Provide mitigation ideas appropriate for non-crypto and crypto blocks and verifica...
Author: Assistant
Category: fpga-asic-design | Model: gpt-4o
Design a hybrid verification approach: minimal directed tests for bring-up, constrained-random for coverage, and targeted stress tests for corner cases. Include how to triage failures quickly.
Author: Assistant
Category: fpga-asic-design | Model: gpt-4o
For FPGA targets, propose a placement strategy: pblocks/regions, timing-driven placement constraints, and critical path isolation. Include how to balance routability vs performance.
Author: Assistant
Category: fpga-asic-design | Model: gpt-4o
Create a fixed-point methodology: range analysis, quantization noise, saturation/rounding policy, and unit tests against a floating reference. Provide a plan to minimize bits while meeting accuracy.
Author: Assistant
Category: fpga-asic-design | Model: gpt-4o
Design an AXI4 subsystem plan: outstanding transactions, ID width, arbitration policy, QoS, burst alignment, and backpressure behavior. Provide a verification checklist for ordering, deadlock, and thr...
Author: Assistant
Category: fpga-asic-design | Model: gpt-4o
Create best practices for SystemVerilog interfaces: modports, clocking blocks, packing, and synthesis/tool compatibility. Provide a style guide and examples for streaming buses.
Author: Assistant
Category: fpga-asic-design | Model: gpt-4o
Design hardware for rational resampling or multi-rate pipelines: buffering, phase accumulators, and control. Provide a fixed-point plan and test strategy against a reference model.
Author: Assistant
Category: fpga-asic-design | Model: gpt-4o
Design glitch-free muxing for clocks/enables: safe selection, handshakes, and integrated cells (ASIC). Provide recommended RTL/structural patterns and verification steps.
Author: Assistant
Category: fpga-asic-design | Model: gpt-4o
Propose ECC integration: SECDED choice, syndrome handling, scrub policy, and latency impact. Provide RTL interface patterns and verification checks including injected faults.
Author: Assistant
Category: fpga-asic-design | Model: gpt-4o
Given interface constraints, choose optimal bus width and burst sizes to maximize effective bandwidth. Include alignment rules, packing/unpacking costs, and a microbenchmark plan.
Author: Assistant
Category: fpga-asic-design | Model: gpt-4o
For a pipelined design with dependencies, propose hazard management: scoreboarding, bypassing, stalling rules, and correctness proof sketch. Include test scenarios and assertions.
Author: Assistant
Category: fpga-asic-design | Model: gpt-4o
Design a BFM strategy to accelerate debug: minimal BFMs for smoke tests, full BFMs for protocol correctness, and a layering approach. Include reproducibility and seed handling rules.
Author: Assistant
Category: fpga-asic-design | Model: gpt-4o
Propose an interrupt strategy: aggregation, prioritization, masking, and latency optimization. Provide a register map approach and verification plan for storms and lost interrupts.
Author: Assistant
Category: fpga-asic-design | Model: gpt-4o
Define a coverage plan: functional coverage points, cross coverage, corner-case scenarios, and coverage closure strategy. Provide a template that ties coverage to requirements.
Author: Assistant
Category: fpga-asic-design | Model: gpt-4o
Propose a formal plan: key safety properties, liveness properties, assume-guarantee boundaries, and abstraction strategies. Provide example SVAs and cover properties for control FSMs.
Author: Assistant
Category: fpga-asic-design | Model: gpt-4o
Create a FIFO sizing method (based on producer/consumer rates and burstiness). Provide RTL patterns for sync and async FIFOs, full/empty logic correctness, gray counters, and verification scenarios.
Author: Assistant
Category: fpga-asic-design | Model: gpt-4o
Define a standard valid/ready contract for your design: latency, skid buffers, combinational paths, and backpressure. Provide reference RTL templates and SVAs to enforce protocol correctness.
Author: Assistant
Category: fpga-asic-design | Model: gpt-4o
Create a latency budget and pipeline plan for a multi-stage datapath. Include register placement strategy, control alignment, valid/ready propagation, bubble handling, and a method to keep cycle-accur...
Author: Assistant
Category: fpga-asic-design | Model: gpt-4o
Design hardware security boundaries: secure/non-secure access, key storage assumptions, access control in CSR/DMA, and audit signals. Provide a threat model and verification plan for bypass attempts.
Author: Assistant
Category: fpga-asic-design | Model: gpt-4o
For an FPGA target, propose how to map multiplies/adds to DSP blocks vs LUTs, including bit-width planning, packing, pipeline stages, and timing considerations. Provide a resource estimation template.
Author: Assistant
Category: fpga-asic-design | Model: gpt-4o
Create a partitioning plan for FPGA prototyping/emulation: clocking, transactors, memory modeling, and performance vs visibility tradeoffs. Provide a checklist for achieving stable bring-up.
Author: Assistant
Category: fpga-asic-design | Model: gpt-4o
Given target throughput, latency, power, area, and interfaces, produce a trade study that maps requirements to candidate microarchitectures (pipeline vs iterative, SIMD vs systolic, cache vs scratchpa...
Author: Assistant
Category: fpga-asic-design | Model: gpt-4o
Create a bring-up checklist for high-speed links: pin planning, constraints, clocking, eye considerations, loopback tests, and debug instrumentation. Include a staged validation plan.
Author: Assistant
Category: fpga-asic-design | Model: gpt-4o
Given access patterns and bandwidth, decide between SRAM macro, regfile, and distributed RAM (FPGA). Provide latency/area/power tradeoffs, banking strategy, and verification implications.
Author: Assistant
Category: fpga-asic-design | Model: gpt-4o
Design a robust reset strategy for FPGA and ASIC: global vs local resets, sequencing, POR behavior, scan considerations, and safe deassertion across domains. Include RTL patterns and verification appr...
Author: Assistant
Category: fpga-asic-design | Model: gpt-4o
Create a senior-level design review checklist: correctness, protocol rigor, CDC/reset, timing risk, scalability, testability, documentation, and verification completeness. Provide a rubric and red fla...
Author: Assistant
Category: fpga-asic-design | Model: gpt-4o
Design a clocking plan: PLL/MMCM usage, derived clocks, jitter budget, clock gating, and crossing strategy. Provide how to document clock assumptions for STA and verification.
Author: Assistant
Category: fpga-asic-design | Model: gpt-4o
Map a compute kernel onto a systolic array: dataflow, tiling, reuse, boundary handling, and I/O streaming. Provide RTL-level interface plan and performance model.
Author: Assistant
Category: fpga-asic-design | Model: gpt-4o
Explain how to write congestion-resilient RTL: hierarchy planning, bus structuring, avoiding wide mux cones, and controlling fanout. Provide a checklist and refactoring patterns.
Author: Assistant
Category: fpga-asic-design | Model: gpt-4o
Create a packetization/framing scheme for high-speed links: framing, CRC, alignment markers, credit/backpressure, and error recovery. Provide RTL module boundaries and test plan.
Author: Assistant
Category: fpga-asic-design | Model: gpt-4o
Propose a golden model approach: bit-exact C/Python model vs tolerance-based checking, when each is appropriate, and how to keep models consistent with RTL changes. Include sync strategy and versionin...
Author: Assistant
Category: fpga-asic-design | Model: gpt-4o
Design an error handling approach: ECC/parity, timeout detection, error registers, interrupt strategy, and safe recovery states. Provide a taxonomy of errors and verification scenarios.
Author: Assistant
Category: fpga-asic-design | Model: gpt-4o
Create a credit-based flow control scheme: credit accounting, initialization, loss recovery, and deadlock avoidance. Provide RTL templates and SVAs to ensure credits never underflow/overflow.
Author: Assistant
Category: fpga-asic-design | Model: gpt-4o
Provide RTL coding patterns that enable retiming: avoiding unnecessary async resets, minimizing combinational loops, using clear pipeline boundaries. Include examples and pitfalls.
Author: Assistant
Category: fpga-asic-design | Model: gpt-4o
Propose a clock gating strategy: where to gate, safe enable conditions, integrated clock gating cells, and verification. Include power/timing tradeoffs and common pitfalls.
Author: Assistant
Category: fpga-asic-design | Model: gpt-4o
Given workload and bandwidth, choose cache hierarchy vs scratchpad. Provide coherence implications, DMA model, and verification complexity tradeoffs. Include performance modeling approach.
Author: Assistant
Category: fpga-asic-design | Model: gpt-4o
Provide criteria to decide HLS vs hand RTL: performance ceilings, maintainability, verification burden, and toolchain maturity. Include a recommended hybrid flow and how to validate HLS output.
Author: Assistant
Category: fpga-asic-design | Model: gpt-4o
Design a CI pipeline for hardware: lint rules, CDC checks, reset checks, basic formal proofs, and regression simulation tiers. Include pass/fail gates and artifact retention for debug.
Author: Assistant
Category: fpga-asic-design | Model: gpt-4o
Create an X-prop strategy: when to use X-optimism vs pessimism, initialization, and how to avoid hiding bugs. Provide simulation flags guidance and SVA patterns to detect X-leaks.
Author: Assistant
Category: fpga-asic-design | Model: gpt-4o
Design a CRC module (parameterized polynomial/width): streaming interface, latency options, and reset behavior. Provide SVAs and randomized tests to prove correctness.
Author: Assistant
Category: fpga-asic-design | Model: gpt-4o
Provide a guide for writing parameterized RTL safely: type parameters, generate usage, width inference, and avoiding accidental truncation. Include lint rules and unit test patterns.
Author: Assistant
Category: fpga-asic-design | Model: gpt-4o
Design a banking scheme: address mapping, interleaving, conflict detection, and scheduling. Include a proof argument for worst-case bandwidth and a microbenchmark plan to validate.
Author: Assistant
Category: fpga-asic-design | Model: gpt-4o
Generate a reusable SVA library for: valid/ready, FIFO correctness, credit-based flow control, and AXI protocol subsets. Include guidelines for binding, disabling, and X-prop handling.
Author: Assistant
Category: fpga-asic-design | Model: gpt-4o
Create a DFT plan: scan insertion strategy, test points, MBIST for SRAMs, and how to ensure observability/controllability for critical state machines. Provide early RTL guidelines to avoid DFT pain.
Author: Assistant
Category: fpga-asic-design | Model: gpt-4o
Design a DMA engine: descriptor format, scatter/gather, burst strategy, alignment handling, error reporting, and security boundaries. Provide test plan including corner cases and stress tests.
Author: Assistant
Category: fpga-asic-design | Model: gpt-4o
Create a CSR spec template: address map, field semantics, reset values, side effects, atomicity, and reserved bits. Include guidelines for forward compatibility and software driver alignment.
Author: Assistant
Category: fpga-asic-design | Model: gpt-4o
Provide a method to estimate area and power early: toggle-rate assumptions, macro estimates, resource mapping, and sensitivity analysis. Include how to reconcile estimates with synthesis results.
Author: Assistant
Category: fpga-asic-design | Model: gpt-4o
Design arbitration for shared resources: round-robin, fixed priority, aging, QoS-aware. Provide a method to evaluate fairness, tail latency, and starvation risk with traces.
Author: Assistant
Category: fpga-asic-design | Model: gpt-4o
Draft a BOM cost model for Suginami prototypes: make/buy split, MOQ effects, duty/shipping. Provide a price-down plan and supplier RFQ template.
Author: Assistant
Category: cost-engineering-NPI | Model: gpt-4o
Draft a handoff playbook from Suginami labs to contract manufacturers. Include DFM/DFA checklist, tolerance stack, CTQ list, golden sample criteria, and PPAP-lite docs.
Author: Assistant
Category: new-product-introduction | Model: gpt-4o
Define a two-day plan where ChatGPT writes the PRD and backlog, Cursor scaffolds the app and tests, Antigravity deploys a preview and runs user-journey checks. Output demo script and next-MVP plan.
Author: Assistant
Category: rapid-delivery | Model: gpt-4o
Propose a simulation-first strategy: CFD for wings and exteriors, multibody for suspension, click-models for magazine UX. Define model fidelity tiers and validation plans.
Author: Assistant
Category: systems-engineering-sim | Model: gpt-4o
Design a pre-silicon validation flow using emulation and FPGA protos: partition strategy, speed/visibility tradeoffs, trace buffers, stimulus generation, coverage closure, and HW/SW co-verification mi...
Author: Assistant
Category: chip-design | Model: gpt-4
You are a mechanical lead. Compare SLA, SLS, MJF, FDM, CNC for a functional prototype: tolerances, surface finish, strength, lead time, cost, post-processing. Recommend path to EVT/DVT with gate crite...
Author: tsubasa
Category: mechanical | Model: gpt-4o