Showing results for "async-fifo"
Create a time zone strategy: async-first norms, overlap windows, handoff checklists, and meeting hygiene. Include a schedule template for teams spanning USA/Europe/Asia.
Author: Assistant
Category: global-business-advice | Model: gpt-4o
Create a FIFO sizing method (based on producer/consumer rates and burstiness). Provide RTL patterns for sync and async FIFOs, full/empty logic correctness, gray counters, and verification scenarios.
Author: Assistant
Category: fpga-asic-design | Model: gpt-4o
Generate a CDC audit checklist: async FIFO design, synchronizer placement, handshake protocols, reset crossings, multi-bit control, and metastability risk scoring. Provide recommended assertions and t...
Author: Assistant
Category: fpga-asic-design | Model: gpt-4o
Audit my messaging habits. Propose rules for when to use Slack vs email vs meeting. Provide templates for concise messages and a weekly cleanup routine.
Author: Assistant
Category: soft-skills | Model: GPT-5.2
Design a robust reset strategy for FPGA and ASIC: global vs local resets, sequencing, POR behavior, scan considerations, and safe deassertion across domains. Include RTL patterns and verification appr...
Author: Assistant
Category: fpga-asic-design | Model: gpt-4o
Design 5 lightweight rituals for remote teams (async wins, weekly demo, gratitude thread). Include how to keep them from feeling forced.
Author: Assistant
Category: soft-skills | Model: GPT-5.2
Create a disagreement framework: clarify intent, show evidence, propose alternatives, and align on goals. Provide scripts for meetings and async messages, with cultural tuning by region.
Author: Assistant
Category: global-business-advice | Model: gpt-4o
Provide RTL coding patterns that enable retiming: avoiding unnecessary async resets, minimizing combinational loops, using clear pipeline boundaries. Include examples and pitfalls.
Author: Assistant
Category: fpga-asic-design | Model: gpt-4o
Generate a reusable SVA library for: valid/ready, FIFO correctness, credit-based flow control, and AXI protocol subsets. Include guidelines for binding, disabling, and X-prop handling.
Author: Assistant
Category: fpga-asic-design | Model: gpt-4o
Provide a deadlock analysis method: dependency graph, buffer ordering, and escape paths. Include a checklist for AXI + DMA + multiple FIFOs systems.
Author: Assistant
Category: fpga-asic-design | Model: gpt-4o
Audit a calendar and convert eligible meetings to async. Provide email/Slack templates, decision logs, and criteria to cancel, compress, or cluster meetings.
Author: Assistant
Category: time-management | Model: gpt-4o
ChatGPT proposes caching/connection pool/async patterns; Cursor wires benchmark harness; Antigravity runs comparative tests and recommends configs per environment.
Author: Assistant
Category: backend-optimization | Model: gpt-4o
Design an Agile operating model across Taiwan and USA time zones: overlapping hours, sprint rituals, async specs, Definition of Ready/Done, and bilingual ticket hygiene.
Author: Assistant
Category: software-process | Model: gpt-4o
You are a systems tutor. Create a 6-week Rust roadmap for engineers moving from C/C++. Cover ownership/borrowing, traits, async, FFI, and building a CLI + service. Provide weekly labs, benchmarks vs C...
Author: Assistant
Category: software | Model: gpt-4o