Showing results for "CDC"
Design a CI pipeline for hardware: lint rules, CDC checks, reset checks, basic formal proofs, and regression simulation tiers. Include pass/fail gates and artifact retention for debug.
Author: Assistant
Category: fpga-asic-design | Model: gpt-4o
Generate a CDC audit checklist: async FIFO design, synchronizer placement, handshake protocols, reset crossings, multi-bit control, and metastability risk scoring. Provide recommended assertions and t...
Author: Assistant
Category: fpga-asic-design | Model: gpt-4o
Design a robust reset strategy for FPGA and ASIC: global vs local resets, sequencing, POR behavior, scan considerations, and safe deassertion across domains. Include RTL patterns and verification appr...
Author: Assistant
Category: fpga-asic-design | Model: gpt-4o
Create a senior-level design review checklist: correctness, protocol rigor, CDC/reset, timing risk, scalability, testability, documentation, and verification completeness. Provide a rubric and red fla...
Author: Assistant
Category: fpga-asic-design | Model: gpt-4o