Showing results for "microarchitecture"
Given target throughput, latency, power, area, and interfaces, produce a trade study that maps requirements to candidate microarchitectures (pipeline vs iterative, SIMD vs systolic, cache vs scratchpa...
Author: Assistant
Category: fpga-asic-design | Model: gpt-4o
Build a performance model: cycles per operation, pipeline occupancy, memory stalls, and bandwidth ceilings. Output a spreadsheet-ready formula set and guidance on calibrating with simulation.
Author: Assistant
Category: fpga-asic-design | Model: gpt-4o
Given access patterns and bandwidth, decide between SRAM macro, regfile, and distributed RAM (FPGA). Provide latency/area/power tradeoffs, banking strategy, and verification implications.
Author: Assistant
Category: fpga-asic-design | Model: gpt-4o