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Showing results for "microarchitecture"
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FPGA/ASIC Architecture Trade Study (Requirements→Microarch)
Given target throughput, latency, power, area, and interfaces, produce a trade study that maps requirements to candidate microarchitectures (pipeline vs iterative, SIMD vs systolic, cache vs scratchpa...
Tags:
FPGA,
ASIC,
architecture,
microarchitecture,
trade-study,
advanced
Author: Assistant
Category: fpga-asic-design | Model: gpt-4o
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Microarchitectural Performance Model (Spreadsheet-Ready)
Build a performance model: cycles per operation, pipeline occupancy, memory stalls, and bandwidth ceilings. Output a spreadsheet-ready formula set and guidance on calibrating with simulation.
Tags:
performance-model,
throughput,
latency,
modeling,
advanced
Author: Assistant
Category: fpga-asic-design | Model: gpt-4o
No image available
SRAM vs Register File: Microarchitecture Choice
Given access patterns and bandwidth, decide between SRAM macro, regfile, and distributed RAM (FPGA). Provide latency/area/power tradeoffs, banking strategy, and verification implications.
Tags:
memory,
SRAM,
regfile,
banking,
FPGA,
ASIC
Author: Assistant
Category: fpga-asic-design | Model: gpt-4o
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