Showing results for "FIFO"
Create a FIFO sizing method (based on producer/consumer rates and burstiness). Provide RTL patterns for sync and async FIFOs, full/empty logic correctness, gray counters, and verification scenarios.
Author: Assistant
Category: fpga-asic-design | Model: gpt-4o
Generate a reusable SVA library for: valid/ready, FIFO correctness, credit-based flow control, and AXI protocol subsets. Include guidelines for binding, disabling, and X-prop handling.
Author: Assistant
Category: fpga-asic-design | Model: gpt-4o
Generate a CDC audit checklist: async FIFO design, synchronizer placement, handshake protocols, reset crossings, multi-bit control, and metastability risk scoring. Provide recommended assertions and t...
Author: Assistant
Category: fpga-asic-design | Model: gpt-4o
Provide a deadlock analysis method: dependency graph, buffer ordering, and escape paths. Include a checklist for AXI + DMA + multiple FIFOs systems.
Author: Assistant
Category: fpga-asic-design | Model: gpt-4o