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Showing results for "FIFO"
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FIFO Design: Depth Sizing + Corner Cases
Create a FIFO sizing method (based on producer/consumer rates and burstiness). Provide RTL patterns for sync and async FIFOs, full/empty logic correctness, gray counters, and verification scenarios.
Tags:
FIFO,
buffering,
async,
sync,
verification,
advanced
Author: Assistant
Category: fpga-asic-design | Model: gpt-4o
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SVA Library: Handshake, FIFO, and AXI Assertions
Generate a reusable SVA library for: valid/ready, FIFO correctness, credit-based flow control, and AXI protocol subsets. Include guidelines for binding, disabling, and X-prop handling.
Tags:
SVA,
assertions,
AXI,
FIFO,
verification,
advanced
Author: Assistant
Category: fpga-asic-design | Model: gpt-4o
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Clock Domain Crossing (CDC) Audit Playbook
Generate a CDC audit checklist: async FIFO design, synchronizer placement, handshake protocols, reset crossings, multi-bit control, and metastability risk scoring. Provide recommended assertions and t...
Tags:
CDC,
clock-domains,
async-fifo,
synchronizers,
verification
Author: Assistant
Category: fpga-asic-design | Model: gpt-4o
No image available
Deadlock Analysis for Interconnect + Buffers
Provide a deadlock analysis method: dependency graph, buffer ordering, and escape paths. Include a checklist for AXI + DMA + multiple FIFOs systems.
Tags:
deadlock,
interconnect,
buffers,
AXI,
analysis
Author: Assistant
Category: fpga-asic-design | Model: gpt-4o
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