Showing results for "RTL"
Design a CRC module (parameterized polynomial/width): streaming interface, latency options, and reset behavior. Provide SVAs and randomized tests to prove correctness.
Author: Assistant
Category: fpga-asic-design | Model: gpt-4o
Design a robust reset strategy for FPGA and ASIC: global vs local resets, sequencing, POR behavior, scan considerations, and safe deassertion across domains. Include RTL patterns and verification appr...
Author: Assistant
Category: fpga-asic-design | Model: gpt-4o
Create a FIFO sizing method (based on producer/consumer rates and burstiness). Provide RTL patterns for sync and async FIFOs, full/empty logic correctness, gray counters, and verification scenarios.
Author: Assistant
Category: fpga-asic-design | Model: gpt-4o
Propose a golden model approach: bit-exact C/Python model vs tolerance-based checking, when each is appropriate, and how to keep models consistent with RTL changes. Include sync strategy and versionin...
Author: Assistant
Category: fpga-asic-design | Model: gpt-4o
Create a DFT plan: scan insertion strategy, test points, MBIST for SRAMs, and how to ensure observability/controllability for critical state machines. Provide early RTL guidelines to avoid DFT pain.
Author: Assistant
Category: fpga-asic-design | Model: gpt-4o
Create a packetization/framing scheme for high-speed links: framing, CRC, alignment markers, credit/backpressure, and error recovery. Provide RTL module boundaries and test plan.
Author: Assistant
Category: fpga-asic-design | Model: gpt-4o
Propose ECC integration: SECDED choice, syndrome handling, scrub policy, and latency impact. Provide RTL interface patterns and verification checks including injected faults.
Author: Assistant
Category: fpga-asic-design | Model: gpt-4o
Propose a timing closure loop: constraint philosophy, path grouping, false/multicycle paths, retiming, floorplanning feedback, and ECO strategy. Include a checklist for reading timing reports efficien...
Author: Assistant
Category: fpga-asic-design | Model: gpt-4o
Create a latency budget and pipeline plan for a multi-stage datapath. Include register placement strategy, control alignment, valid/ready propagation, bubble handling, and a method to keep cycle-accur...
Author: Assistant
Category: fpga-asic-design | Model: gpt-4o
Create best practices for SystemVerilog interfaces: modports, clocking blocks, packing, and synthesis/tool compatibility. Provide a style guide and examples for streaming buses.
Author: Assistant
Category: fpga-asic-design | Model: gpt-4o
Create an X-prop strategy: when to use X-optimism vs pessimism, initialization, and how to avoid hiding bugs. Provide simulation flags guidance and SVA patterns to detect X-leaks.
Author: Assistant
Category: fpga-asic-design | Model: gpt-4o
Explain floorplanning impacts (wire delay, congestion) and how RTL choices affect P&R. Provide a feedback loop between block partitioning, hierarchy, and constraints.
Author: Assistant
Category: fpga-asic-design | Model: gpt-4o
Create a credit-based flow control scheme: credit accounting, initialization, loss recovery, and deadlock avoidance. Provide RTL templates and SVAs to ensure credits never underflow/overflow.
Author: Assistant
Category: fpga-asic-design | Model: gpt-4o
Define a standard valid/ready contract for your design: latency, skid buffers, combinational paths, and backpressure. Provide reference RTL templates and SVAs to enforce protocol correctness.
Author: Assistant
Category: fpga-asic-design | Model: gpt-4o
Map a compute kernel onto a systolic array: dataflow, tiling, reuse, boundary handling, and I/O streaming. Provide RTL-level interface plan and performance model.
Author: Assistant
Category: fpga-asic-design | Model: gpt-4o
Design glitch-free muxing for clocks/enables: safe selection, handshakes, and integrated cells (ASIC). Provide recommended RTL/structural patterns and verification steps.
Author: Assistant
Category: fpga-asic-design | Model: gpt-4o
Create a side-channel awareness checklist: data-dependent switching, timing variability, and observable control flow. Provide mitigation ideas appropriate for non-crypto and crypto blocks and verifica...
Author: Assistant
Category: fpga-asic-design | Model: gpt-4o
Provide a method to estimate area and power early: toggle-rate assumptions, macro estimates, resource mapping, and sensitivity analysis. Include how to reconcile estimates with synthesis results.
Author: Assistant
Category: fpga-asic-design | Model: gpt-4o
Provide criteria to decide HLS vs hand RTL: performance ceilings, maintainability, verification burden, and toolchain maturity. Include a recommended hybrid flow and how to validate HLS output.
Author: Assistant
Category: fpga-asic-design | Model: gpt-4o
Provide a guide for writing parameterized RTL safely: type parameters, generate usage, width inference, and avoiding accidental truncation. Include lint rules and unit test patterns.
Author: Assistant
Category: fpga-asic-design | Model: gpt-4o
Explain how to write congestion-resilient RTL: hierarchy planning, bus structuring, avoiding wide mux cones, and controlling fanout. Provide a checklist and refactoring patterns.
Author: Assistant
Category: fpga-asic-design | Model: gpt-4o
Provide RTL coding patterns that enable retiming: avoiding unnecessary async resets, minimizing combinational loops, using clear pipeline boundaries. Include examples and pitfalls.
Author: Assistant
Category: fpga-asic-design | Model: gpt-4o
Create an i18n checklist for web/app: UTF-8, zh-TW locale, pluralization, truncation, font fallbacks (Noto Sans TC), RTL-safety check, and screenshot diffing.
Author: Assistant
Category: frontend-quality | Model: gpt-4o