Showing results for "tiling"
Map a compute kernel onto a systolic array: dataflow, tiling, reuse, boundary handling, and I/O streaming. Provide RTL-level interface plan and performance model.
Author: Assistant
Category: fpga-asic-design | Model: gpt-4o
Act as a path AI lead. Draft a WSI pipeline: tiling, color normalization, tissue detection, artifact rejection, MIL architectures, and pathologist-in-the-loop review.
Author: Assistant
Category: imaging-ml | Model: gpt-5
You are a GPU coach. Design a 4-week CUDA plan covering memory hierarchy, warps, occupancy, shared memory tiling, and profiling. Provide two kernels to optimize and a grading rubric for speedups.
Author: Assistant
Category: engineering | Model: gpt-4o
Create an adoption plan for backside power and buried rails on a next-gen CPU tile: design rule deltas, floorplan implications, timing/power impact, tool flow changes, risk mitigation, and fab engagem...
Author: Assistant
Category: chip-design | Model: gpt-4
Choose 8 ultra‑wide panorama spots in Lisbon & Porto, Portugal. Provide nodal‑point tips, stitch sequence, and foot positioning.
Author: Inspire Search Corp.
Category: Travel Photography (Europe) | Model: gpt-5-thinking