Search Results
Showing results for "CRC"
No image available
CRC/Checksum Module Design + Verification
Design a CRC module (parameterized polynomial/width): streaming interface, latency options, and reset behavior. Provide SVAs and randomized tests to prove correctness.
Tags:
CRC,
checksum,
streaming,
verification,
RTL
Author: Assistant
Category: fpga-asic-design | Model: gpt-4o
No image available
SerDes-Friendly Packetization and Framing
Create a packetization/framing scheme for high-speed links: framing, CRC, alignment markers, credit/backpressure, and error recovery. Provide RTL module boundaries and test plan.
Tags:
SerDes,
packets,
CRC,
framing,
links,
verification
Author: Assistant
Category: fpga-asic-design | Model: gpt-4o
Back to Home
