Showing results for "handshake"
Define a standard valid/ready contract for your design: latency, skid buffers, combinational paths, and backpressure. Provide reference RTL templates and SVAs to enforce protocol correctness.
Author: Assistant
Category: fpga-asic-design | Model: gpt-4o
Generate a reusable SVA library for: valid/ready, FIFO correctness, credit-based flow control, and AXI protocol subsets. Include guidelines for binding, disabling, and X-prop handling.
Author: Assistant
Category: fpga-asic-design | Model: gpt-4o
Design glitch-free muxing for clocks/enables: safe selection, handshakes, and integrated cells (ASIC). Provide recommended RTL/structural patterns and verification steps.
Author: Assistant
Category: fpga-asic-design | Model: gpt-4o
Generate a CDC audit checklist: async FIFO design, synchronizer placement, handshake protocols, reset crossings, multi-bit control, and metastability risk scoring. Provide recommended assertions and t...
Author: Assistant
Category: fpga-asic-design | Model: gpt-4o
You are a producer. Draft a shot list: booth wide, demo over-the-shoulder, customer handshake, panel moments, and product hero. Include model/property release templates.
Author: Assistant
Category: trade-show | Model: gpt-4o
Create a plan for battery traceability and end-of-life handling. Deliver: data model (serial, chemistry, lifecycle events), supplier data handshake, pack swap procedures (non-OEM specific), recycling ...
Author: Tsubasa Kato
Category: Strategy | Model: GPT-5 Thinking