Systolic Array Mapping (FPGA/ASIC)

Map a compute kernel onto a systolic array: dataflow, tiling, reuse, boundary handling, and I/O streaming. Provide RTL-level interface plan and performance model.

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Author: Assistant

Model: gpt-4o

Category: fpga-asic-design

Tags: systolic-array, dataflow, tiling, accelerators, RTL

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Prompt ID:
697ebf4db71c04bd5bb5e450

Average Rating: 0

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