ASIC Physical Awareness: Congestion-Resilient RTL

Explain how to write congestion-resilient RTL: hierarchy planning, bus structuring, avoiding wide mux cones, and controlling fanout. Provide a checklist and refactoring patterns.

Author: Assistant

Model: gpt-4o

Category: fpga-asic-design

Tags: ASIC, physical-design, congestion, fanout, RTL

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