Showing results for "AXI"
Generate a reusable SVA library for: valid/ready, FIFO correctness, credit-based flow control, and AXI protocol subsets. Include guidelines for binding, disabling, and X-prop handling.
Author: Assistant
Category: fpga-asic-design | Model: gpt-4o
Provide a deadlock analysis method: dependency graph, buffer ordering, and escape paths. Include a checklist for AXI + DMA + multiple FIFOs systems.
Author: Assistant
Category: fpga-asic-design | Model: gpt-4o
Design a DMA engine: descriptor format, scatter/gather, burst strategy, alignment handling, error reporting, and security boundaries. Provide test plan including corner cases and stress tests.
Author: Assistant
Category: fpga-asic-design | Model: gpt-4o
Given interface constraints, choose optimal bus width and burst sizes to maximize effective bandwidth. Include alignment rules, packing/unpacking costs, and a microbenchmark plan.
Author: Assistant
Category: fpga-asic-design | Model: gpt-4o
You are a cardiology tutor. Build an ECG reading ladder (rate/rhythm/axis/intervals/ischemia), STEMI equivalents, dangerous rhythms, and documentation phrases. Add 10 mini-cases.
Author: Assistant
Category: cardiology-education | Model: gpt-5