Explore Prompts

Build a reliability budget: device degradation models, BTI guardbands, HCI stress points, TDDB oxide limits, EM lifetimes, and burn-in strategy. Provide a reliability dashboard and field-return feedback loop.

Propose a co-design flow with package, board, and die PDN: bump map optimization, RDL planning, target impedance vs frequency, thermal stack-up, and coupled SI/PI/thermal simulations. Include signoff targets and lab correlation plan.

Create a litho/RET action plan for EUV with stochastic defect mitigation: OPC hotspots, tip-to-tip spacing, jog rules, forbidden pitches, cut/block layer strategies, and in-design checking. Provide a hotspot taxonomy and fix library.

Design a yield-ramp methodology: defect density assumptions, critical area analysis, redundancy strategies, pattern-matching for systematic defects, Pareto dashboards, and wafer map analytics. Include an 8-week improvement plan with KPIs.

Develop a DFT plan: scan compression goals, LBIST architecture, MBIST algorithms for SRAM/ROM, boundary scan, JTAG access, test time/cost model, and fault coverage targets. Provide patterns and bring-up steps.

For a 12-bit SAR ADC and PLL, provide layout tactics: common-centroid matching, guard rings, substrate isolation, well taps, shielding, dummy fills, coupling control, and latch-up prevention. Include post-layout extraction checks and acceptance thresholds.

Outline a custom SRAM plan (6T/8T): read/write stability analysis, Vmin targets, assist techniques, redundancy/repair, ECC options, leakage control, and BIST. Provide SPICE corners, Monte Carlo setup, and signoff criteria.

Create an HBM3E integration plan: stack selection, channel topology, timing margins, package escape routing, SI/PI simulations, PDN target impedance, thermal throttling strategy, and test hooks. Output checklists and key acceptance metrics.

Propose a chiplet SoC using UCIe 1.1 over 2.5D interposer: partitioning rationale, die-to-die bandwidth/latency budget, PHY choices, protocol mapping, cache-coherency options, test strategy, and yield/cost model. Provide a bring-up checklist and risks.

Write a power architecture using UPF with 3 voltage islands, DVFS, and retention strategies. Provide power-state tables, isolation/level-shifter rules, retention flop mapping, and power-sequencing timing. Output UPF snippets and a verification checklist.

Produce a timing closure plan across slow/fast corners using POCV/SSTA. Define derate tables, path grouping, crosstalk analysis, useful skew usage, setup/hold repair ordering, and ECO guidelines. Include a metrics dashboard (WNS/TNS/violators) and convergence criteria.

Draft a DRC/LVS closure strategy under EUV and multi-patterning rules. Include hotspot classes, recommended routing rules, antenna fixes, via redundancy, density/slotting, guard rings, and signoff waiver protocol. Return a checklist and a Pareto of typical violations with fix recipes.