Explore Prompts

Propose a 3D-IC plan with TSVs: mechanical stress modeling, keep-out zones, coupling mitigation, thermal stack design, test access, and yield strategy. Include co-simulation setup and acceptance thresholds.

Draft a safety and reliability plan: FIT targets, FMEDA, ASIL decomposition, safety mechanisms, aging stress, ESD/EMC design, and qualification flow (AEC-Q100). Provide safety case artifacts and test plan.

Create an adoption plan for backside power and buried rails on a next-gen CPU tile: design rule deltas, floorplan implications, timing/power impact, tool flow changes, risk mitigation, and fab engagement checklist.

Define a library characterization plan at low voltage (0.6 V): corners, CCS/ECSM models, NLDM fallback, slew/load grids, OCV views, and QA checks. Provide Liberty snippets and validation tests.

Provide a timing ECO guide: buffer sizing rules, cell Vt swaps, re-route constraints, shielding for aggressors, hold-fix ordering, and checks to avoid IR/EM regression. Include a before/after metrics template.

Compare SAR, pipeline, and sigma-delta ADCs for a sensor hub. Include FoM, resolution/SNR targets, sampling rate, power, area, calibration needs, and DFT hooks. Output a recommendation with risk log and bring-up plan.

Create a PLL plan: loop filter design, VCO selection, fractional-N spur mitigation, jitter decomposition, phase noise spec allocation, and supply-noise rejection. Provide simulation setups and acceptance limits.

Propose a mmWave beamformer: phase shifter topology, PA/LNA linearity targets, NF, LO distribution, antenna-in-package constraints, calibration loops, and EVM/ACL metrics. Provide layout isolation guidelines.

Outline a high-speed SerDes design: channel specs, CTLE/DFE equalization, CDR architecture, TX FIR taps, jitter budget, compliance masks, and IBIS-AMI modeling. Include lab validation steps and BER targets.

Design a pre-silicon validation flow using emulation and FPGA protos: partition strategy, speed/visibility tradeoffs, trace buffers, stimulus generation, coverage closure, and HW/SW co-verification milestones.

Create a silicon security plan: logic locking insertion points, scan chain protections, PUF selection and enrollment, side-channel mitigation, secure boot root-of-trust, and anti-tamper sensors. Provide verification tests and threat model.

Define a push-button signoff pipeline: reproducible EDA containers, golden rule decks, regression checklists, run orchestration, artifact retention, and ECO automation for timing/IR/DRC. Output a CI/CD-style YAML skeleton.