Explore Prompts

Create a PLL plan: loop filter design, VCO selection, fractional-N spur mitigation, jitter decomposition, phase noise spec allocation, and supply-noise rejection. Provide simulation setups and acceptance limits.

Propose a mmWave beamformer: phase shifter topology, PA/LNA linearity targets, NF, LO distribution, antenna-in-package constraints, calibration loops, and EVM/ACL metrics. Provide layout isolation guidelines.

Outline a high-speed SerDes design: channel specs, CTLE/DFE equalization, CDR architecture, TX FIR taps, jitter budget, compliance masks, and IBIS-AMI modeling. Include lab validation steps and BER targets.

Design a pre-silicon validation flow using emulation and FPGA protos: partition strategy, speed/visibility tradeoffs, trace buffers, stimulus generation, coverage closure, and HW/SW co-verification milestones.

Create a silicon security plan: logic locking insertion points, scan chain protections, PUF selection and enrollment, side-channel mitigation, secure boot root-of-trust, and anti-tamper sensors. Provide verification tests and threat model.

Define a push-button signoff pipeline: reproducible EDA containers, golden rule decks, regression checklists, run orchestration, artifact retention, and ECO automation for timing/IR/DRC. Output a CI/CD-style YAML skeleton.

Build a reliability budget: device degradation models, BTI guardbands, HCI stress points, TDDB oxide limits, EM lifetimes, and burn-in strategy. Provide a reliability dashboard and field-return feedback loop.

Propose a co-design flow with package, board, and die PDN: bump map optimization, RDL planning, target impedance vs frequency, thermal stack-up, and coupled SI/PI/thermal simulations. Include signoff targets and lab correlation plan.

Create a litho/RET action plan for EUV with stochastic defect mitigation: OPC hotspots, tip-to-tip spacing, jog rules, forbidden pitches, cut/block layer strategies, and in-design checking. Provide a hotspot taxonomy and fix library.

Design a yield-ramp methodology: defect density assumptions, critical area analysis, redundancy strategies, pattern-matching for systematic defects, Pareto dashboards, and wafer map analytics. Include an 8-week improvement plan with KPIs.

Develop a DFT plan: scan compression goals, LBIST architecture, MBIST algorithms for SRAM/ROM, boundary scan, JTAG access, test time/cost model, and fault coverage targets. Provide patterns and bring-up steps.

For a 12-bit SAR ADC and PLL, provide layout tactics: common-centroid matching, guard rings, substrate isolation, well taps, shielding, dummy fills, coupling control, and latch-up prevention. Include post-layout extraction checks and acceptance thresholds.