Explore Prompts

Outline a custom SRAM plan (6T/8T): read/write stability analysis, Vmin targets, assist techniques, redundancy/repair, ECC options, leakage control, and BIST. Provide SPICE corners, Monte Carlo setup, and signoff criteria.

Create an HBM3E integration plan: stack selection, channel topology, timing margins, package escape routing, SI/PI simulations, PDN target impedance, thermal throttling strategy, and test hooks. Output checklists and key acceptance metrics.

Propose a chiplet SoC using UCIe 1.1 over 2.5D interposer: partitioning rationale, die-to-die bandwidth/latency budget, PHY choices, protocol mapping, cache-coherency options, test strategy, and yield/cost model. Provide a bring-up checklist and risks.

Write a power architecture using UPF with 3 voltage islands, DVFS, and retention strategies. Provide power-state tables, isolation/level-shifter rules, retention flop mapping, and power-sequencing timing. Output UPF snippets and a verification checklist.

Produce a timing closure plan across slow/fast corners using POCV/SSTA. Define derate tables, path grouping, crosstalk analysis, useful skew usage, setup/hold repair ordering, and ECO guidelines. Include a metrics dashboard (WNS/TNS/violators) and convergence criteria.

Draft a DRC/LVS closure strategy under EUV and multi-patterning rules. Include hotspot classes, recommended routing rules, antenna fixes, via redundancy, density/slotting, guard rings, and signoff waiver protocol. Return a checklist and a Pareto of typical violations with fix recipes.

Create a power integrity plan using backside power delivery and buried power rails. Include PDN topology, stripe pitch, via stacking, decap budgeting, vectorless vs vector-based IR analysis, EM rules, and signoff thresholds. Provide a mitigation matrix ranked by PPA impact.

Design a CTS plan that balances skew, latency, and power for a 1.2 GHz domain with multiple clock gating islands. Include buffer/inverter choices, mesh vs spine tradeoffs, useful-skew targets, OCV derates, hold-fix strategy, and post-CTS ECO flow. Output a table of constraints and acceptance criteria.

Act as a PnR lead at 2nm. Propose a floorplan strategy for a large SoC with multiple GAA CPU/GPU clusters: die size estimate, aspect ratio, macro placement heuristics, channel widths, hierarchy partitioning, pin planning, blockage strategy, and congestion risk map. Provide a step-by-step checklist and a CSV of floorplan constraints.

Provide a 15-experiment matrix of performance marketing growth hacks tailored to Asia, Europe, and the USA. For each region include channel, hypothesis, creative example, audience segment, KPI, budget range, and success criteria so teams can run prioritized experiments in parallel.

Lay out a growth-hack focused on SEO and content syndication for US audiences. Recommend topic clusters, pillar pages, syndication partners (newsletters, industry sites), backlink tactics, tracking setup, and a 6-month roadmap to double organic traffic.

Create a growth-hack combining localized launch events and a targeted PR blitz to gain traction in US metros. Include event formats, press outreach templates, journalist lists by vertical, timeline, expected media impressions, and follow-up conversion tactics.