SVA Library: Handshake, FIFO, and AXI Assertions
Generate a reusable SVA library for: valid/ready, FIFO correctness, credit-based flow control, and AXI protocol subsets. Include guidelines for binding, disabling, and X-prop handling.
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Formal Verification Plan for Control Logic
Propose a formal plan: key safety properties, liveness properties, assume-guarantee boundaries, and abstraction strategies. Provide example SVAs and cover properties for control FSMs.
Fixed-Point Design: Wordlength Optimization
Create a fixed-point methodology: range analysis, quantization noise, saturation/rounding policy, and unit tests against a floating reference. Provide a plan to minimize bits while meeting accuracy.
DSP Block Utilization Strategy (FPGA)
For an FPGA target, propose how to map multiplies/adds to DSP blocks vs LUTs, including bit-width planning, packing, pipeline stages, and timing considerations. Provide a resource estimation template.
Systolic Array Mapping (FPGA/ASIC)
Map a compute kernel onto a systolic array: dataflow, tiling, reuse, boundary handling, and I/O streaming. Provide RTL-level interface plan and performance model.
Memory Banking + Conflict Avoidance Strategy
Design a banking scheme: address mapping, interleaving, conflict detection, and scheduling. Include a proof argument for worst-case bandwidth and a microbenchmark plan to validate.
SRAM vs Register File: Microarchitecture Choice
Given access patterns and bandwidth, decide between SRAM macro, regfile, and distributed RAM (FPGA). Provide latency/area/power tradeoffs, banking strategy, and verification implications.
FIFO Design: Depth Sizing + Corner Cases
Create a FIFO sizing method (based on producer/consumer rates and burstiness). Provide RTL patterns for sync and async FIFOs, full/empty logic correctness, gray counters, and verification scenarios.
Valid/Ready Protocol Formalization
Define a standard valid/ready contract for your design: latency, skid buffers, combinational paths, and backpressure. Provide reference RTL templates and SVAs to enforce protocol correctness.
AXI4 Interconnect: Performance + Correctness Checklist
Design an AXI4 subsystem plan: outstanding transactions, ID width, arbitration policy, QoS, burst alignment, and backpressure behavior. Provide a verification checklist for ordering, deadlock, and throughput.
Constraint Authoring: SDC Patterns That Scale
Write scalable SDC patterns: generated clocks, clock uncertainty, I/O constraints, clock groups, and exceptions. Include best practices to avoid over-constraining and how to validate constraints with reports.
Timing Closure Strategy: RTL→Synthesis→P&R Loop
Propose a timing closure loop: constraint philosophy, path grouping, false/multicycle paths, retiming, floorplanning feedback, and ECO strategy. Include a checklist for reading timing reports efficiently.