ECC Integration for SRAMs and Buses
Propose ECC integration: SECDED choice, syndrome handling, scrub policy, and latency impact. Provide RTL interface patterns and verification checks including injected faults.
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Error Handling Architecture: Detect, Report, Recover
Design an error handling approach: ECC/parity, timeout detection, error registers, interrupt strategy, and safe recovery states. Provide a taxonomy of errors and verification scenarios.
Bus Width and Burst Optimization
Given interface constraints, choose optimal bus width and burst sizes to maximize effective bandwidth. Include alignment rules, packing/unpacking costs, and a microbenchmark plan.
Deadlock Analysis for Interconnect + Buffers
Provide a deadlock analysis method: dependency graph, buffer ordering, and escape paths. Include a checklist for AXI + DMA + multiple FIFOs systems.
Credit-Based Flow Control Design
Create a credit-based flow control scheme: credit accounting, initialization, loss recovery, and deadlock avoidance. Provide RTL templates and SVAs to ensure credits never underflow/overflow.
Arbitration Policies: Fairness vs Latency
Design arbitration for shared resources: round-robin, fixed priority, aging, QoS-aware. Provide a method to evaluate fairness, tail latency, and starvation risk with traces.
Hazard Management: Scoreboarding vs Stalling
For a pipelined design with dependencies, propose hazard management: scoreboarding, bypassing, stalling rules, and correctness proof sketch. Include test scenarios and assertions.
Retiming-Friendly RTL Patterns
Provide RTL coding patterns that enable retiming: avoiding unnecessary async resets, minimizing combinational loops, using clear pipeline boundaries. Include examples and pitfalls.
Floorplanning Concepts for RTL Engineers
Explain floorplanning impacts (wire delay, congestion) and how RTL choices affect P&R. Provide a feedback loop between block partitioning, hierarchy, and constraints.
Area/Power Estimation Early in RTL
Provide a method to estimate area and power early: toggle-rate assumptions, macro estimates, resource mapping, and sensitivity analysis. Include how to reconcile estimates with synthesis results.
Microarchitectural Performance Model (Spreadsheet-Ready)
Build a performance model: cycles per operation, pipeline occupancy, memory stalls, and bandwidth ceilings. Output a spreadsheet-ready formula set and guidance on calibrating with simulation.
Emulation/FPGA Prototyping: Partitioning Plan
Create a partitioning plan for FPGA prototyping/emulation: clocking, transactors, memory modeling, and performance vs visibility tradeoffs. Provide a checklist for achieving stable bring-up.