Explore Prompts

Design a hybrid verification approach: minimal directed tests for bring-up, constrained-random for coverage, and targeted stress tests for corner cases. Include how to triage failures quickly.

Create best practices for SystemVerilog interfaces: modports, clocking blocks, packing, and synthesis/tool compatibility. Provide a style guide and examples for streaming buses.

Provide a guide for writing parameterized RTL safely: type parameters, generate usage, width inference, and avoiding accidental truncation. Include lint rules and unit test patterns.

Design a CRC module (parameterized polynomial/width): streaming interface, latency options, and reset behavior. Provide SVAs and randomized tests to prove correctness.

Create a packetization/framing scheme for high-speed links: framing, CRC, alignment markers, credit/backpressure, and error recovery. Provide RTL module boundaries and test plan.

Design hardware for rational resampling or multi-rate pipelines: buffering, phase accumulators, and control. Provide a fixed-point plan and test strategy against a reference model.

Design glitch-free muxing for clocks/enables: safe selection, handshakes, and integrated cells (ASIC). Provide recommended RTL/structural patterns and verification steps.

Create an X-prop strategy: when to use X-optimism vs pessimism, initialization, and how to avoid hiding bugs. Provide simulation flags guidance and SVA patterns to detect X-leaks.

Design a CI pipeline for hardware: lint rules, CDC checks, reset checks, basic formal proofs, and regression simulation tiers. Include pass/fail gates and artifact retention for debug.

Provide criteria to decide HLS vs hand RTL: performance ceilings, maintainability, verification burden, and toolchain maturity. Include a recommended hybrid flow and how to validate HLS output.

Create a side-channel awareness checklist: data-dependent switching, timing variability, and observable control flow. Provide mitigation ideas appropriate for non-crypto and crypto blocks and verification considerations.

Design hardware security boundaries: secure/non-secure access, key storage assumptions, access control in CSR/DMA, and audit signals. Provide a threat model and verification plan for bypass attempts.