Showing results for "hierarchy"
Explain floorplanning impacts (wire delay, congestion) and how RTL choices affect P&R. Provide a feedback loop between block partitioning, hierarchy, and constraints.
Author: Assistant
Category: fpga-asic-design | Model: gpt-4o
Explain how to write congestion-resilient RTL: hierarchy planning, bus structuring, avoiding wide mux cones, and controlling fanout. Provide a checklist and refactoring patterns.
Author: Assistant
Category: fpga-asic-design | Model: gpt-4o
Given workload and bandwidth, choose cache hierarchy vs scratchpad. Provide coherence implications, DMA model, and verification complexity tradeoffs. Include performance modeling approach.
Author: Assistant
Category: fpga-asic-design | Model: gpt-4o
Select a typographic palette (serif/sans/mono) and define hierarchy, optical sizes, and language coverage. Provide do/don’t rules and accessibility contrast targets.
Author: Assistant
Category: typography-guidelines | Model: gpt-4o
Create a dataviz style guide: chart selection rules, gridlines, annotation hierarchy, and colorblind-safe palettes. Provide chart templates and QA checklist.
Author: Assistant
Category: data-visualization-standards | Model: gpt-4o
You are a clinical ethics guide. Provide consent/assent steps, capacity checks, surrogate hierarchies, and documentation phrases. Include sample ethics consult questions.
Author: Assistant
Category: ethics-law | Model: gpt-5
You are a GPU coach. Design a 4-week CUDA plan covering memory hierarchy, warps, occupancy, shared memory tiling, and profiling. Provide two kernels to optimize and a grading rubric for speedups.
Author: Assistant
Category: engineering | Model: gpt-4o
Act as a PnR lead at 2nm. Propose a floorplan strategy for a large SoC with multiple GAA CPU/GPU clusters: die size estimate, aspect ratio, macro placement heuristics, channel widths, hierarchy partit...
Author: Assistant
Category: chip-design | Model: gpt-4