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Showing results for "topology"
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Multi-Agent Topology: Hub-and-Spoke vs Mesh
Compare multi-agent topologies (hub-and-spoke, mesh, hierarchical). Recommend which to use by task type and risk profile, with failure-mode analysis.
Tags:
multi-agent,
topology,
coordination,
architecture,
risk
Author: Assistant
Category: agent-architecture | Model: GPT-5.2
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CAN Bus and Network Fault Triage
Design a CAN/LIN/network fault triage workflow for modern vehicles: topology, termination checks, DTC grouping, module wake/sleep behavior, bus voltage, and when to suspect wiring vs module faults.
Tags:
CAN-bus,
LIN,
vehicle-network,
diagnostics,
electrical
Author: Assistant
Category: vehicle-engineering-mechanics | Model: GPT-5.2
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MoE Routing & Load Balancing
Design an expert-parallel MoE serving topology: gate calibration, capacity factor, expert sharding, and interconnect constraints (NVLink/IB). Provide hot-spot diagnostics and expert-drop policies for ...
Tags:
LLM,
MoE,
experts,
routing,
capacity,
NVLink,
InfiniBand
Author: Assistant
Category: distributed-systems-LLM | Model: gpt-4o
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Lightweighting with Cost Guardrails
Propose a 5% mass reduction through materials and topology optimization. Include cost delta caps, supplier readiness, and corrosion strategy. Output a part-by-part plan.
Tags:
automotive,
lightweighting,
cost,
materials,
optimization
Author: Assistant
Category: value-engineering-auto | Model: gpt-4o
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mmWave RFIC Beamformer Array
Propose a mmWave beamformer: phase shifter topology, PA/LNA linearity targets, NF, LO distribution, antenna-in-package constraints, calibration loops, and EVM/ACL metrics. Provide layout isolation gui...
Tags:
IC,
RFIC,
mmWave,
beamforming,
AiP,
calibration
Author: Assistant
Category: chip-design | Model: gpt-4
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HBM3E Integration SI/PI Checklist
Create an HBM3E integration plan: stack selection, channel topology, timing margins, package escape routing, SI/PI simulations, PDN target impedance, thermal throttling strategy, and test hooks. Outpu...
Tags:
IC,
HBM3E,
SI,
PI,
packaging,
thermal
Author: Assistant
Category: chip-design | Model: gpt-4
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IR Drop and EM Co-Optimization (BSPDN)
Create a power integrity plan using backside power delivery and buried power rails. Include PDN topology, stripe pitch, via stacking, decap budgeting, vectorless vs vector-based IR analysis, EM rules,...
Tags:
IC,
PDN,
IR-drop,
EM,
BSPDN,
buried-power-rail
Author: Assistant
Category: chip-design | Model: gpt-4
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P&ID-like Schematic Lite
Draft a simplified P&ID-style schematic for a boiler feedwater loop. Provide symbol list, connection rules, and a Graphviz DOT example to render the topology.
Tags:
industrial|pid|boiler|graphviz|dot
Author: Curioforce Corp. Corp.
Category: Industrial Visualization | Model: gpt-5-thinking
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CAD/Topology: Chair Leg Optimization
Design a topology optimization plan for a chair leg under seated loads. Deliver: load cases, constraints, density method, KPIs (mass, compliance), smooth/print workflow, fatigue screen. Output: steps,...
Tags:
cad,
topology,
lightweight,
furniture,
additive
Author: Tsubasa Kato
Category: Simulation | Model: GPT-5 Thinking
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