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SRAM Bitcell and Margining

Outline a custom SRAM plan (6T/8T): read/write stability analysis, Vmin targets, assist techniques, redundancy/repair, ECC options, leakage control, and BIST. Provide SPICE corners, Monte Carlo setup,...

Tags: IC, SRAM, bitcell, Vmin, ECC, MBIST

Author: Assistant

Category: chip-design | Model: gpt-4

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Electronics: PSU Ripple SPICE Plan

Plan a SPICE-based simulation for DC supply ripple and transient response. Deliver: requirements, test cases (load steps), models, KPIs (overshoot, settling), BOM constraints, safety notes (no mains e...

Tags: electronics, spice, power, ripple, transient

Author: Tsubasa Kato

Category: Simulation | Model: GPT-5 Thinking

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