Prompt Cards

Build a performance model: cycles per operation, pipeline occupancy, memory stalls, and bandwidth ceilings. Output a spreadsheet-ready formula set and guidance on calibrating with simulation.

Create a partitioning plan for FPGA prototyping/emulation: clocking, transactors, memory modeling, and performance vs visibility tradeoffs. Provide a checklist for achieving stable bring-up.

Design a BFM strategy to accelerate debug: minimal BFMs for smoke tests, full BFMs for protocol correctness, and a layering approach. Include reproducibility and seed handling rules.

Create a CSR spec template: address map, field semantics, reset values, side effects, atomicity, and reserved bits. Include guidelines for forward compatibility and software driver alignment.

Propose an interrupt strategy: aggregation, prioritization, masking, and latency optimization. Provide a register map approach and verification plan for storms and lost interrupts.

Design a DMA engine: descriptor format, scatter/gather, burst strategy, alignment handling, error reporting, and security boundaries. Provide test plan including corner cases and stress tests.

Given workload and bandwidth, choose cache hierarchy vs scratchpad. Provide coherence implications, DMA model, and verification complexity tradeoffs. Include performance modeling approach.

Create a DFT plan: scan insertion strategy, test points, MBIST for SRAMs, and how to ensure observability/controllability for critical state machines. Provide early RTL guidelines to avoid DFT pain.

Propose a clock gating strategy: where to gate, safe enable conditions, integrated clock gating cells, and verification. Include power/timing tradeoffs and common pitfalls.

Design a clocking plan: PLL/MMCM usage, derived clocks, jitter budget, clock gating, and crossing strategy. Provide how to document clock assumptions for STA and verification.

Create a bring-up checklist for high-speed links: pin planning, constraints, clocking, eye considerations, loopback tests, and debug instrumentation. Include a staged validation plan.

Propose a golden model approach: bit-exact C/Python model vs tolerance-based checking, when each is appropriate, and how to keep models consistent with RTL changes. Include sync strategy and versioning.