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ASIC Physical Awareness: Congestion-Resilient RTL
Explain how to write congestion-resilient RTL: hierarchy planning, bus structuring, avoiding wide mux cones, and controlling fanout. Provide a checklist and refactoring patterns.
Tags: ASIC, physical-design, congestion, fanout, RTL
Author: Assistant
Created at: 2026-01-06 00:00:00
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FPGA Timing: Placement Constraints and Pblocks
For FPGA targets, propose a placement strategy: pblocks/regions, timing-driven placement constraints, and critical path isolation. Include how to balance routability vs performance.
Tags: FPGA, placement, pblocks, timing, implementation
Author: Assistant
Created at: 2026-01-06 00:00:00
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Testbench Acceleration: Directed + Random Hybrid
Design a hybrid verification approach: minimal directed tests for bring-up, constrained-random for coverage, and targeted stress tests for corner cases. Include how to triage failures quickly.
Tags: verification, strategy, directed, constrained-random, debug
Author: Assistant
Created at: 2026-01-06 00:00:00
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SystemVerilog Interfaces + Modports Best Practices
Create best practices for SystemVerilog interfaces: modports, clocking blocks, packing, and synthesis/tool compatibility. Provide a style guide and examples for streaming buses.
Tags: SystemVerilog, interfaces, modports, RTL, style-guide
Author: Assistant
Created at: 2026-01-06 00:00:00
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Parameterized RTL: Avoiding Generate-Block Footguns
Provide a guide for writing parameterized RTL safely: type parameters, generate usage, width inference, and avoiding accidental truncation. Include lint rules and unit test patterns.
Tags: parameterization, RTL, generate, lint, advanced
Author: Assistant
Created at: 2026-01-06 00:00:00
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CRC/Checksum Module Design + Verification
Design a CRC module (parameterized polynomial/width): streaming interface, latency options, and reset behavior. Provide SVAs and randomized tests to prove correctness.
Tags: CRC, checksum, streaming, verification, RTL
Author: Assistant
Created at: 2026-01-06 00:00:00
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SerDes-Friendly Packetization and Framing
Create a packetization/framing scheme for high-speed links: framing, CRC, alignment markers, credit/backpressure, and error recovery. Provide RTL module boundaries and test plan.
Tags: SerDes, packets, CRC, framing, links, verification
Author: Assistant
Created at: 2026-01-06 00:00:00
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Multi-Rate Systems: Rational Resampling Hardware
Design hardware for rational resampling or multi-rate pipelines: buffering, phase accumulators, and control. Provide a fixed-point plan and test strategy against a reference model.
Tags: multi-rate, DSP, resampling, fixed-point, verification
Author: Assistant
Created at: 2026-01-06 00:00:00
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Glitch-Free Clock/Enable Muxing
Design glitch-free muxing for clocks/enables: safe selection, handshakes, and integrated cells (ASIC). Provide recommended RTL/structural patterns and verification steps.
Tags: clock-mux, glitch-free, ASIC, RTL, verification
Author: Assistant
Created at: 2026-01-06 00:00:00
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X-Propagation Strategy and Unknown Handling
Create an X-prop strategy: when to use X-optimism vs pessimism, initialization, and how to avoid hiding bugs. Provide simulation flags guidance and SVA patterns to detect X-leaks.
Tags: X-prop, simulation, verification, RTL, SVA
Author: Assistant
Created at: 2026-01-06 00:00:00
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Lint + CDC + Formal in CI: Practical Pipeline
Design a CI pipeline for hardware: lint rules, CDC checks, reset checks, basic formal proofs, and regression simulation tiers. Include pass/fail gates and artifact retention for debug.
Tags: CI, lint, CDC, formal, regression, EDA
Author: Assistant
Created at: 2026-01-06 00:00:00
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High-Level Synthesis (HLS) vs Hand RTL Decision
Provide criteria to decide HLS vs hand RTL: performance ceilings, maintainability, verification burden, and toolchain maturity. Include a recommended hybrid flow and how to validate HLS output.
Tags: HLS, RTL, methodology, verification, performance
Author: Assistant
Created at: 2026-01-06 00:00:00
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