Prompt Cards

Define a coverage plan: functional coverage points, cross coverage, corner-case scenarios, and coverage closure strategy. Provide a template that ties coverage to requirements.

Design a UVM environment: agents, scoreboards, reference models, sequence layering, coverage model, and CI integration. Include best practices for reproducibility and debug speed.

Generate a reusable SVA library for: valid/ready, FIFO correctness, credit-based flow control, and AXI protocol subsets. Include guidelines for binding, disabling, and X-prop handling.

Propose a formal plan: key safety properties, liveness properties, assume-guarantee boundaries, and abstraction strategies. Provide example SVAs and cover properties for control FSMs.

Create a fixed-point methodology: range analysis, quantization noise, saturation/rounding policy, and unit tests against a floating reference. Provide a plan to minimize bits while meeting accuracy.

For an FPGA target, propose how to map multiplies/adds to DSP blocks vs LUTs, including bit-width planning, packing, pipeline stages, and timing considerations. Provide a resource estimation template.

Map a compute kernel onto a systolic array: dataflow, tiling, reuse, boundary handling, and I/O streaming. Provide RTL-level interface plan and performance model.

Design a banking scheme: address mapping, interleaving, conflict detection, and scheduling. Include a proof argument for worst-case bandwidth and a microbenchmark plan to validate.

Given access patterns and bandwidth, decide between SRAM macro, regfile, and distributed RAM (FPGA). Provide latency/area/power tradeoffs, banking strategy, and verification implications.

Create a FIFO sizing method (based on producer/consumer rates and burstiness). Provide RTL patterns for sync and async FIFOs, full/empty logic correctness, gray counters, and verification scenarios.

Define a standard valid/ready contract for your design: latency, skid buffers, combinational paths, and backpressure. Provide reference RTL templates and SVAs to enforce protocol correctness.

Design an AXI4 subsystem plan: outstanding transactions, ID width, arbitration policy, QoS, burst alignment, and backpressure behavior. Provide a verification checklist for ordering, deadlock, and throughput.