Prompt Cards

Given workload and bandwidth, choose cache hierarchy vs scratchpad. Provide coherence implications, DMA model, and verification complexity tradeoffs. Include performance modeling approach.

Create a DFT plan: scan insertion strategy, test points, MBIST for SRAMs, and how to ensure observability/controllability for critical state machines. Provide early RTL guidelines to avoid DFT pain.

Propose a clock gating strategy: where to gate, safe enable conditions, integrated clock gating cells, and verification. Include power/timing tradeoffs and common pitfalls.

Design a clocking plan: PLL/MMCM usage, derived clocks, jitter budget, clock gating, and crossing strategy. Provide how to document clock assumptions for STA and verification.

Create a bring-up checklist for high-speed links: pin planning, constraints, clocking, eye considerations, loopback tests, and debug instrumentation. Include a staged validation plan.

Propose a golden model approach: bit-exact C/Python model vs tolerance-based checking, when each is appropriate, and how to keep models consistent with RTL changes. Include sync strategy and versioning.

Define a coverage plan: functional coverage points, cross coverage, corner-case scenarios, and coverage closure strategy. Provide a template that ties coverage to requirements.

Design a UVM environment: agents, scoreboards, reference models, sequence layering, coverage model, and CI integration. Include best practices for reproducibility and debug speed.

Generate a reusable SVA library for: valid/ready, FIFO correctness, credit-based flow control, and AXI protocol subsets. Include guidelines for binding, disabling, and X-prop handling.

Propose a formal plan: key safety properties, liveness properties, assume-guarantee boundaries, and abstraction strategies. Provide example SVAs and cover properties for control FSMs.

Create a fixed-point methodology: range analysis, quantization noise, saturation/rounding policy, and unit tests against a floating reference. Provide a plan to minimize bits while meeting accuracy.

For an FPGA target, propose how to map multiplies/adds to DSP blocks vs LUTs, including bit-width planning, packing, pipeline stages, and timing considerations. Provide a resource estimation template.