Prompt Cards

Map a compute kernel onto a systolic array: dataflow, tiling, reuse, boundary handling, and I/O streaming. Provide RTL-level interface plan and performance model.

Design a banking scheme: address mapping, interleaving, conflict detection, and scheduling. Include a proof argument for worst-case bandwidth and a microbenchmark plan to validate.

Given access patterns and bandwidth, decide between SRAM macro, regfile, and distributed RAM (FPGA). Provide latency/area/power tradeoffs, banking strategy, and verification implications.

Create a FIFO sizing method (based on producer/consumer rates and burstiness). Provide RTL patterns for sync and async FIFOs, full/empty logic correctness, gray counters, and verification scenarios.

Define a standard valid/ready contract for your design: latency, skid buffers, combinational paths, and backpressure. Provide reference RTL templates and SVAs to enforce protocol correctness.

Design an AXI4 subsystem plan: outstanding transactions, ID width, arbitration policy, QoS, burst alignment, and backpressure behavior. Provide a verification checklist for ordering, deadlock, and throughput.

Write scalable SDC patterns: generated clocks, clock uncertainty, I/O constraints, clock groups, and exceptions. Include best practices to avoid over-constraining and how to validate constraints with reports.

Propose a timing closure loop: constraint philosophy, path grouping, false/multicycle paths, retiming, floorplanning feedback, and ECO strategy. Include a checklist for reading timing reports efficiently.

Create a power intent plan: power domains, isolation, retention, level shifters, and power state sequencing. Provide a UPF/CPF concept spec and integration risks for verification and signoff.

Design a robust reset strategy for FPGA and ASIC: global vs local resets, sequencing, POR behavior, scan considerations, and safe deassertion across domains. Include RTL patterns and verification approach.

Generate a CDC audit checklist: async FIFO design, synchronizer placement, handshake protocols, reset crossings, multi-bit control, and metastability risk scoring. Provide recommended assertions and typical failure modes.

Create a latency budget and pipeline plan for a multi-stage datapath. Include register placement strategy, control alignment, valid/ready propagation, bubble handling, and a method to keep cycle-accurate documentation.