Prompt Cards

Create a packetization/framing scheme for high-speed links: framing, CRC, alignment markers, credit/backpressure, and error recovery. Provide RTL module boundaries and test plan.

Design hardware for rational resampling or multi-rate pipelines: buffering, phase accumulators, and control. Provide a fixed-point plan and test strategy against a reference model.

Design glitch-free muxing for clocks/enables: safe selection, handshakes, and integrated cells (ASIC). Provide recommended RTL/structural patterns and verification steps.

Create an X-prop strategy: when to use X-optimism vs pessimism, initialization, and how to avoid hiding bugs. Provide simulation flags guidance and SVA patterns to detect X-leaks.

Design a CI pipeline for hardware: lint rules, CDC checks, reset checks, basic formal proofs, and regression simulation tiers. Include pass/fail gates and artifact retention for debug.

Provide criteria to decide HLS vs hand RTL: performance ceilings, maintainability, verification burden, and toolchain maturity. Include a recommended hybrid flow and how to validate HLS output.

Create a side-channel awareness checklist: data-dependent switching, timing variability, and observable control flow. Provide mitigation ideas appropriate for non-crypto and crypto blocks and verification considerations.

Design hardware security boundaries: secure/non-secure access, key storage assumptions, access control in CSR/DMA, and audit signals. Provide a threat model and verification plan for bypass attempts.

Propose ECC integration: SECDED choice, syndrome handling, scrub policy, and latency impact. Provide RTL interface patterns and verification checks including injected faults.

Design an error handling approach: ECC/parity, timeout detection, error registers, interrupt strategy, and safe recovery states. Provide a taxonomy of errors and verification scenarios.

Given interface constraints, choose optimal bus width and burst sizes to maximize effective bandwidth. Include alignment rules, packing/unpacking costs, and a microbenchmark plan.

Provide a deadlock analysis method: dependency graph, buffer ordering, and escape paths. Include a checklist for AXI + DMA + multiple FIFOs systems.