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Timing ECO Cookbook (Minimal PPA Hit)

Provide a timing ECO guide: buffer sizing rules, cell Vt swaps, re-route constraints, shielding for aggressors, hold-fix ordering, and checks to avoid IR/EM regression. Include a before/after metrics ...

Tags: IC, timing, ECO, SI, cell-sizing, Vt-swap

Author: Assistant

Category: chip-design | Model: gpt-4

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Analog/Mixed-Signal Layout Best Practices

For a 12-bit SAR ADC and PLL, provide layout tactics: common-centroid matching, guard rings, substrate isolation, well taps, shielding, dummy fills, coupling control, and latch-up prevention. Include ...

Tags: IC, AMS, layout, ADC, PLL, matching

Author: Assistant

Category: chip-design | Model: gpt-4

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