Explore Prompts

For a pipelined design with dependencies, propose hazard management: scoreboarding, bypassing, stalling rules, and correctness proof sketch. Include test scenarios and assertions.

Provide RTL coding patterns that enable retiming: avoiding unnecessary async resets, minimizing combinational loops, using clear pipeline boundaries. Include examples and pitfalls.

Explain floorplanning impacts (wire delay, congestion) and how RTL choices affect P&R. Provide a feedback loop between block partitioning, hierarchy, and constraints.

Provide a method to estimate area and power early: toggle-rate assumptions, macro estimates, resource mapping, and sensitivity analysis. Include how to reconcile estimates with synthesis results.

Build a performance model: cycles per operation, pipeline occupancy, memory stalls, and bandwidth ceilings. Output a spreadsheet-ready formula set and guidance on calibrating with simulation.

Create a partitioning plan for FPGA prototyping/emulation: clocking, transactors, memory modeling, and performance vs visibility tradeoffs. Provide a checklist for achieving stable bring-up.

Design a BFM strategy to accelerate debug: minimal BFMs for smoke tests, full BFMs for protocol correctness, and a layering approach. Include reproducibility and seed handling rules.

Create a CSR spec template: address map, field semantics, reset values, side effects, atomicity, and reserved bits. Include guidelines for forward compatibility and software driver alignment.

Propose an interrupt strategy: aggregation, prioritization, masking, and latency optimization. Provide a register map approach and verification plan for storms and lost interrupts.

Design a DMA engine: descriptor format, scatter/gather, burst strategy, alignment handling, error reporting, and security boundaries. Provide test plan including corner cases and stress tests.

Given workload and bandwidth, choose cache hierarchy vs scratchpad. Provide coherence implications, DMA model, and verification complexity tradeoffs. Include performance modeling approach.

Create a DFT plan: scan insertion strategy, test points, MBIST for SRAMs, and how to ensure observability/controllability for critical state machines. Provide early RTL guidelines to avoid DFT pain.