Explore Prompts

Create a 10-minute home safety audit: hazards to fix, basic supplies to add, where to store items, and how to reduce injury risk. Include a simple checklist for Europe/Asia/USA/Africa housing styles.

Design a 72-hour go-bag checklist tailored to me (solo, couple, family with kids, elderly, pets). Include region-appropriate items, documents, and medication considerations. Provide a lightweight version for commuters and travelers.

Create a calm, practical emergency readiness plan for my region (Europe/Asia/USA/Africa) and living situation (apartment/house/dorm). Include: realistic risks, low-cost preparations, a 72-hour kit checklist, and a monthly maintenance routine. Use reassuring language and avoid sensational framing.

Create a senior-level design review checklist: correctness, protocol rigor, CDC/reset, timing risk, scalability, testability, documentation, and verification completeness. Provide a rubric and red flags.

Explain how to write congestion-resilient RTL: hierarchy planning, bus structuring, avoiding wide mux cones, and controlling fanout. Provide a checklist and refactoring patterns.

For FPGA targets, propose a placement strategy: pblocks/regions, timing-driven placement constraints, and critical path isolation. Include how to balance routability vs performance.

Design a hybrid verification approach: minimal directed tests for bring-up, constrained-random for coverage, and targeted stress tests for corner cases. Include how to triage failures quickly.

Create best practices for SystemVerilog interfaces: modports, clocking blocks, packing, and synthesis/tool compatibility. Provide a style guide and examples for streaming buses.

Provide a guide for writing parameterized RTL safely: type parameters, generate usage, width inference, and avoiding accidental truncation. Include lint rules and unit test patterns.

Design a CRC module (parameterized polynomial/width): streaming interface, latency options, and reset behavior. Provide SVAs and randomized tests to prove correctness.

Create a packetization/framing scheme for high-speed links: framing, CRC, alignment markers, credit/backpressure, and error recovery. Provide RTL module boundaries and test plan.

Design hardware for rational resampling or multi-rate pipelines: buffering, phase accumulators, and control. Provide a fixed-point plan and test strategy against a reference model.