Glitch-Free Clock/Enable Muxing
Design glitch-free muxing for clocks/enables: safe selection, handshakes, and integrated cells (ASIC). Provide recommended RTL/structural patterns and verification steps.
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X-Propagation Strategy and Unknown Handling
Create an X-prop strategy: when to use X-optimism vs pessimism, initialization, and how to avoid hiding bugs. Provide simulation flags guidance and SVA patterns to detect X-leaks.
Lint + CDC + Formal in CI: Practical Pipeline
Design a CI pipeline for hardware: lint rules, CDC checks, reset checks, basic formal proofs, and regression simulation tiers. Include pass/fail gates and artifact retention for debug.
High-Level Synthesis (HLS) vs Hand RTL Decision
Provide criteria to decide HLS vs hand RTL: performance ceilings, maintainability, verification burden, and toolchain maturity. Include a recommended hybrid flow and how to validate HLS output.
Side-Channel Risk Awareness for RTL Engineers
Create a side-channel awareness checklist: data-dependent switching, timing variability, and observable control flow. Provide mitigation ideas appropriate for non-crypto and crypto blocks and verification considerations.
Security Boundaries in Hardware: Trust Zones
Design hardware security boundaries: secure/non-secure access, key storage assumptions, access control in CSR/DMA, and audit signals. Provide a threat model and verification plan for bypass attempts.
ECC Integration for SRAMs and Buses
Propose ECC integration: SECDED choice, syndrome handling, scrub policy, and latency impact. Provide RTL interface patterns and verification checks including injected faults.
Error Handling Architecture: Detect, Report, Recover
Design an error handling approach: ECC/parity, timeout detection, error registers, interrupt strategy, and safe recovery states. Provide a taxonomy of errors and verification scenarios.
Bus Width and Burst Optimization
Given interface constraints, choose optimal bus width and burst sizes to maximize effective bandwidth. Include alignment rules, packing/unpacking costs, and a microbenchmark plan.
Deadlock Analysis for Interconnect + Buffers
Provide a deadlock analysis method: dependency graph, buffer ordering, and escape paths. Include a checklist for AXI + DMA + multiple FIFOs systems.
Credit-Based Flow Control Design
Create a credit-based flow control scheme: credit accounting, initialization, loss recovery, and deadlock avoidance. Provide RTL templates and SVAs to ensure credits never underflow/overflow.
Arbitration Policies: Fairness vs Latency
Design arbitration for shared resources: round-robin, fixed priority, aging, QoS-aware. Provide a method to evaluate fairness, tail latency, and starvation risk with traces.