Clock Gating and Enable Strategy (ASIC)
Propose a clock gating strategy: where to gate, safe enable conditions, integrated clock gating cells, and verification. Include power/timing tradeoffs and common pitfalls.
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Clocking Architecture: PLL/MMCM and Jitter Budget
Design a clocking plan: PLL/MMCM usage, derived clocks, jitter budget, clock gating, and crossing strategy. Provide how to document clock assumptions for STA and verification.
High-Speed I/O Bring-Up Checklist (FPGA Prototyping)
Create a bring-up checklist for high-speed links: pin planning, constraints, clocking, eye considerations, loopback tests, and debug instrumentation. Include a staged validation plan.
Golden Model Strategy: Bit-Exact vs Tolerant
Propose a golden model approach: bit-exact C/Python model vs tolerance-based checking, when each is appropriate, and how to keep models consistent with RTL changes. Include sync strategy and versioning.
Coverage-Driven Verification: What to Measure
Define a coverage plan: functional coverage points, cross coverage, corner-case scenarios, and coverage closure strategy. Provide a template that ties coverage to requirements.
UVM Testbench Architecture for a Complex IP
Design a UVM environment: agents, scoreboards, reference models, sequence layering, coverage model, and CI integration. Include best practices for reproducibility and debug speed.
SVA Library: Handshake, FIFO, and AXI Assertions
Generate a reusable SVA library for: valid/ready, FIFO correctness, credit-based flow control, and AXI protocol subsets. Include guidelines for binding, disabling, and X-prop handling.
Formal Verification Plan for Control Logic
Propose a formal plan: key safety properties, liveness properties, assume-guarantee boundaries, and abstraction strategies. Provide example SVAs and cover properties for control FSMs.
Fixed-Point Design: Wordlength Optimization
Create a fixed-point methodology: range analysis, quantization noise, saturation/rounding policy, and unit tests against a floating reference. Provide a plan to minimize bits while meeting accuracy.
DSP Block Utilization Strategy (FPGA)
For an FPGA target, propose how to map multiplies/adds to DSP blocks vs LUTs, including bit-width planning, packing, pipeline stages, and timing considerations. Provide a resource estimation template.
Systolic Array Mapping (FPGA/ASIC)
Map a compute kernel onto a systolic array: dataflow, tiling, reuse, boundary handling, and I/O streaming. Provide RTL-level interface plan and performance model.
Memory Banking + Conflict Avoidance Strategy
Design a banking scheme: address mapping, interleaving, conflict detection, and scheduling. Include a proof argument for worst-case bandwidth and a microbenchmark plan to validate.