Prompt Cards

You are a GPU coach. Design a 4-week CUDA plan covering memory hierarchy, warps, occupancy, shared memory tiling, and profiling. Provide two kernels to optimize and a grading rubric for speedups.

Act as a performance engineer. Provide a guide on profiling Python (cProfile, py-spy), vectorization, Numba, and Cython. Include memory tips, I/O batching, and a before/after benchmark template.

You are a systems tutor. Create a 6-week Rust roadmap for engineers moving from C/C++. Cover ownership/borrowing, traits, async, FFI, and building a CLI + service. Provide weekly labs, benchmarks vs C, and a template repo structure.

Act as a mentor for students new to AI. Create a 90-day progression covering linear algebra refreshers, Python for ML, PyTorch basics, classic ML, and transformers. Include weekly goals, reading links (generic), coding exercises, and a pass/fail checklist for each week. End with a mini-capstone rubric.

Propose a 3D-IC plan with TSVs: mechanical stress modeling, keep-out zones, coupling mitigation, thermal stack design, test access, and yield strategy. Include co-simulation setup and acceptance thresholds.

Draft a safety and reliability plan: FIT targets, FMEDA, ASIL decomposition, safety mechanisms, aging stress, ESD/EMC design, and qualification flow (AEC-Q100). Provide safety case artifacts and test plan.

Create an adoption plan for backside power and buried rails on a next-gen CPU tile: design rule deltas, floorplan implications, timing/power impact, tool flow changes, risk mitigation, and fab engagement checklist.

Define a library characterization plan at low voltage (0.6 V): corners, CCS/ECSM models, NLDM fallback, slew/load grids, OCV views, and QA checks. Provide Liberty snippets and validation tests.

Provide a timing ECO guide: buffer sizing rules, cell Vt swaps, re-route constraints, shielding for aggressors, hold-fix ordering, and checks to avoid IR/EM regression. Include a before/after metrics template.

Compare SAR, pipeline, and sigma-delta ADCs for a sensor hub. Include FoM, resolution/SNR targets, sampling rate, power, area, calibration needs, and DFT hooks. Output a recommendation with risk log and bring-up plan.

Create a PLL plan: loop filter design, VCO selection, fractional-N spur mitigation, jitter decomposition, phase noise spec allocation, and supply-noise rejection. Provide simulation setups and acceptance limits.

Propose a mmWave beamformer: phase shifter topology, PA/LNA linearity targets, NF, LO distribution, antenna-in-package constraints, calibration loops, and EVM/ACL metrics. Provide layout isolation guidelines.